Assigning a bit in SV Assertion

In reply to ben@SystemVerilog.us:

Hi Ben,

Thanks a lot. That really helped. I tried it out and its working perfectly fine.

Also I did a small experiment. I write ##0 instead of |-> after $rose as shown below:

property data_check;
@(clk) @rose(write_cycle) ##0
first_match(##[1:5] signal_to_check == write_data) #-#
((signal_to_check == write_data) until $rose(write_cycle));
endproperty

Ended up with Assertion errors at every point of time. Why does it happen? Also I need some fundamental understanding regarding the working of |-> , ##0 and #-#. Is there any relevant article for this? That shall be of great help for me.