Verification Academy

Topic	Replies	Views	Activity
Writing to register using absolute address UVM UVM	2	714	July 25, 2022
How to connect analysis port which has different transaction type? UVM UVM , analysis-port-connectionconnect_phase	2	814	July 25, 2022
Calling function inside seq body SystemVerilog SystemVerilog , FunctionArgument	8	860	July 25, 2022
How memory interaction between C Language in SV or UVM UVM SystemVerilog , UVM , assertion , System-Verilog	2	909	July 25, 2022
Features inquiry: Add support for (true) anonymous aggregate data types & packed union with different size members SystemVerilog SystemVerilog	2	649	July 25, 2022
How to resolve the warning "The expression "xaction_1.example_struct.trans" is a member of a packed structure and cannot be used in a solve-before constraint." SystemVerilog SystemVerilog , constraint-randomization , packed-struct , solve-before	1	582	July 25, 2022
Constraint SystemVerilog SystemVerilog	2	459	July 25, 2022
Back to back write read operations Coverage Coverage , functional-coverage-systemverilog	1	589	July 25, 2022
What is the register enumerated field? UVM UVM	1	301	July 25, 2022
Creating a custom array of cover bins Coverage Coverage	12	1684	July 25, 2022
UVM/Guidelines 5.2 Avoid the usage of main_phase from cookbook UVM UVM , run_phase-main_phase	1	448	July 25, 2022
Random constraints SystemVerilog SystemVerilog , constraint , random	1	603	July 25, 2022
Using lock/unlock with STRICT_FIFO arbitration UVM UVM , Sequencer-unlock , UVM_SEQ_ARB_STRICT_FIFO , Sequencer-lock	1	455	July 25, 2022
SystmeVerilog Assertions -> operator SystemVerilog SystemVerilog , assertion , RTL-coverage	1	763	July 24, 2022
How to pass a FIFO/List/queue into a sequence running on an agent which is reactive in it's nature UVM UVM , reactive-agent	0	345	July 24, 2022
Is there a way to request new features for SystemVerilog? SystemVerilog SystemVerilog	2	640	July 24, 2022
I want to set a DUT's signal with a default value without agent instantiation. Which is the best way to do that? UVM UVM	2	541	July 23, 2022
Overriding build_phase UVM UVM , override , build_phase	2	910	July 23, 2022
Constraint solver SystemVerilog SystemVerilog , constraint-randomization , constraint-solver , interdependency-of-variables , constraint-execution	6	5921	July 23, 2022
How to convert a always block in to task SystemVerilog SystemVerilog	5	903	July 22, 2022
Start_item and finish_item SystemVerilog SystemVerilog , function , sequence-item	1	530	July 22, 2022
Control over randomization without using constraint SystemVerilog SystemVerilog , constraint-randomization , Verilog	3	801	July 22, 2022
How to sort a 2D unpacked array SystemVerilog SystemVerilog , sorting , 2Darray	3	2039	July 22, 2022
UVM RAL vertical reuse UVM UVM , UVM-RAL-vertical-reuse	1	427	July 22, 2022
UVM_FATAL in Simulation UVM UVM	4	2073	July 22, 2022
Assertion for id should not change when request is high SystemVerilog SystemVerilog , assertion , stable	2	573	July 22, 2022
How to decide base address & address offset in register map UVM UVM , Cookbook-RegistersComplexAddressMaps	1	768	July 21, 2022
In AXI, at what scenario can use out of order and outstanding transactions SystemVerilog SystemVerilog , AMBA-AXI , model-uvm-reference_model	2	2652	July 20, 2022
Assert is failing before I do assertoff at time 0 in initial block SystemVerilog SystemVerilog , assertion , Assertion-system-verilog , assertoff	2	769	July 20, 2022
Generating an IO interface in a module based on parameter SystemVerilog SystemVerilog , System-Verilog , parameter	0	485	July 19, 2022