Hi,
I have analysis port of x type transaction and implementation port of y type transaction how can I connect this port ?
ex: uvm_analysis_port #(transaction x)x_port;
uvm_analysis_imp_y_port #(transaction y) y_port;
Need to connect these ports
Hi,
I have analysis port of x type transaction and implementation port of y type transaction how can I connect this port ?
ex: uvm_analysis_port #(transaction x)x_port;
uvm_analysis_imp_y_port #(transaction y) y_port;
Need to connect these ports
In reply to sidduamd:
You should read here:
https://verificationacademy.com/cookbook/testbenchbasics
You can use base uvm_sequence_item to represent any transaction from producer you can have x sequence item down cast to base item and pass it to port having base as transaction item. At receiver you can have it cast and used