I have top level verification environment which includes two subsystem environments. Each subsystem environment contains multiple block level environments.
Several block level environments are used for verifying blocks that contain registers.
Because of that, block level environments instantiate UVM register blocks. Dedicated UVM register map is connected to sequencer of agents instantiated under block level environment.
What should be proper way to implement UVM register model on top level?
Should I reuse register blocks from block level environments (by changing sequencer) or should I make new instances in top level environment?
Or maybe there is some exact approach how should UVM RAL be integrated in multi-level environments?