Skip to main content

Upcoming Webinar

Simulating AMD’s next-gen Versal Adaptive SoC devices using QuestaSim

Wednesday, July 24th - 8:00 AM US/Pacific

Learn more and Register!

SIEMENS Verification Academy

Global Site Search

Log In
Register

Topics

The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
UVM

UVM Connect

UVM Framework

SystemVerilog
Simulation & Debug

Simulation

Debug
Methodology & Standards

Coverage

FPGA Verification

Functional Safety

Low Power
Questa Design Solutions

Clock-Domain Crossing

Formal Verification

Reset-Domain Crossing
Verification Management & IP

Verification IQ

Verification IP

Verification Planning
All Topics
Cookbooks

Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
UVM

UVM Basics

UVM Testbench

UVM Configuring a Test Environment

UVM Analysis Components & Techniques

UVM Sequences

UVM Messaging System

UVM Stimulus Techniques

UVM Register Abstraction Layer

UVM Debugging

UVM Connect
Guidelines & Migration

SystemVerilog Coding

SystemVerilog Performance

UVM Coding

UVM Performance

UVM 1800.2

UVM 1.2

OVM to UVM

Deployment

Code Examples
Class Reference

UVM 1.2

UVM 1.1d

UVM 1.1c

UVM 1.1b

UVM 1.1a
Coverage

Coverage Metrics and Process (Theory)

Coverage Examples (Practice)

Appendices
All Content

Browse all content in the Verification Academy
By Type

Article

Cookbook

Resource

Track
By Video

Demo

Session

Webinar
By Tag

SystemVerilog

UVMF

Testbench

Debug
By Audience

Beginner

Intermediate

Advanced
All Content
Forums
Forums

UVM

SystemVerilog

Coverage
By Tags

Assertion

SystemVerilog

Constraint

Sequence

RAL
By Topic Status

By Latest

By Unsolved

By Solved
All Forums
More
Verification Academy

VA Live - Spring Tour

Verification Horizons

About Us

Contact Us
Siemens EDA

Events & Webinars

Verification Horizons Blog

OneSpin

Avery Design Systems
Siemens Learning Center

Learning Memberships

Learning Labs

On-Demand Training

Instructor Led

Badging and Certification

Breadcrumbs

Home

Browse all content in Siemens Verification Academy with the tag Design Optimization

Search Results - 12 results

Filters

Reset All

Filters

Topic

Formal Verification (6)

Questa Design Solutions (3)

Debug (1)

Planning, Measurement and Analysis (1)

Simulation (1)

Content Type

Resource (5)

Session (4)

Seminar (1)

Track (1)

Webinar (1)

Audience

Intermediate (10)

Beginner (1)

Tags

Design Optimization (12)

RTL (8)

Equivalence Checking (5)

Formal Verification (5)

SLEC (5)

Sequential Analysis (5)

Clock Gating (4)

Lint (3)

Low Power (3)

QDS (3)

Debug (2)

Safety Mechanism (2)

Components (1)

Cover Properties (1)

ECO (1)

Japanese (1)

Metrics (1)

Model Checking (1)

Performance (1)

Profiling (1)

Properties (1)

Property Checking (1)

Property Checks (1)

Regression (1)

Simulation (1)

SoC (1)

U2U Europe (1)

VA Live - Westford (1)

VA Live 2024 - El Segundo (1)

VA Live 2024 - Huntsville (1)

VA Live 2024 - San Diego (1)

VA Live 2024 - Westford (1)

Verification IP (1)

Verification Productivity (1)

Show More

Show Less

June 2024

Beyond Speed: Unlocking Productivity in Simulation and Debug
Simulation Jun 12, 2024 Moses Satyasekaran pdf

May 2024

Improving Simulation Performance Utilizing the Visualizer Profiler
Debug May 07, 2024 George Lloyd - Arm Seminar

June 2023

Formal Model Checking Made Easy
Formal Verification Jun 14, 2023 Martin Rowe pdf

September 2021

Improving Initial RTL Quality
Questa Design Solutions Sep 15, 2021 Chris Giles Webinar
Improving Initial RTL Quality | Japanese
Questa Design Solutions Sep 15, 2021 Chris Giles pdf
Improving Initial RTL Quality
Questa Design Solutions Sep 15, 2021 Chris Giles pdf

July 2021

Sequential Logic Equivalence Checking
Formal Verification Jul 06, 2021 Jin Hou Track
SLEC Introduction
Formal Verification Jul 06, 2021 Jin Hou Session
SLEC for Design Optimization
Formal Verification Jul 06, 2021 Jin Hou Session
SLEC for Low Power Clock Gating
Formal Verification Jul 06, 2021 Jin Hou Session
SLEC for Safety Mechanism
Formal Verification Jul 06, 2021 Jin Hou Session

July 2019

Selecting the Most Productive SoC Design Verification Techniques
Planning, Measurement and Analysis Jul 12, 2019 pdf

SIEMENS Siemens Digital Industries Software

Portfolio

Cloud
Mendix
Electronic Design Automation
MindSphere
Insights Hub
Design, Manufacturing and PLM Software
View all portfolio

Explore

Community
Blog
Online Store
Glossary

Siemens

About Us
Careers
Events
News and Press
Case Studies
Partners
Trust Center

Contact

VA - Contact Us
PLM - Contact Us
EDA - Contact Us
Worldwide Offices
Support Center
Give us Feedback
Report piracy

© Siemens 2024

Terms of Use
Privacy Policy
Cookie Statement
DMCA
Whistleblowing