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The Importance of Simulation in the Pursuit of Absolute Speed!
Simulation Apr 02, 2024 Sunil Sahoo link
Questa Check Connect Fact Sheet
Formal Verification Apr 01, 2024 Nicolae Tusinschi pdf
Questa Check Register Fact Sheet
Formal Verification Apr 01, 2024 Nicolae Tusinschi pdf

March 2024

Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
Verification IP Mar 27, 2024 Rick Koster pdf
Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
Verification IP Mar 27, 2024 Rick Koster Webinar
In Memoriam: Chris Spear
SystemVerilog Mar 14, 2024 Tom Fitzpatrick link
New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
Questa Design Solutions Mar 14, 2024 Atul Sharma pdf
New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
Reset-Domain Crossing Mar 14, 2024 Atul Sharma Webinar
Get your free copy of the IEEE 1800-2023 SystemVerilog LRM
SystemVerilog Mar 04, 2024 Dave Rich link
Verification Horizons
Planning, Measurement and Analysis Mar 01, 2024 Tom Fitzpatrick Article
Enhancing PCIe Verification: How to Step Off the Map
Verification IP Mar 01, 2024 Irivinti Shiva Teja - Siemens Eda Article
Tool Assisted Debug in Visualizer
Debug Mar 01, 2024 Richa Jha - Siemens Eda Article
Formal Verification: An Introduction and Exploration of Challenges
Formal Verification Mar 01, 2024 Yusuf Eren - Ankasys Article
Maximize Returns on Your Hardware Emulation Investment with the Veloce Enterprise (ES) App
Acceleration Mar 01, 2024 Chuck Banken, Chenguang Li - Siemens Eda Article
A True Native 64-bit Vedic Multiplier Boosts Performance for Processors, Multi-Cores and DSP
Machine Learning Mar 01, 2024 Lakshya Miglani, Priyanka Gharat, Gopi Srinivas Deepala - Silicon Interfaces mp4
A True Native 64-bit Vedic Multiplier Boosts Performance for Processors, Multi-Cores and DSP
Machine Learning Mar 01, 2024 Lakshya Miglani, Priyanka Gharat, Gopi Srinivas Deepala - Silicon Interfaces Article

February 2024

DVCon 2024 – Verify Real Number Models
UVM - Universal Verification Methodology Feb 26, 2024 Mariam Maurice - Siemens Eda link
UVM Objections at DVCON US 2024 – and Grape Jelly
UVM - Universal Verification Methodology Feb 22, 2024 Rich Edelman link
Comprehensive CXL 3.0 Verification for High-Bandwidth and Low-Latency Connectivity
Verification IP Feb 21, 2024 Chris Browy Webinar
Join us at DVCon for a panel on Generative AI
Machine Learning Feb 14, 2024 Harry Foster link
Functional Verification workflow for Trusted and Assured Microelectronics
Formal Verification Feb 06, 2024 John Hallman Webinar
Functional Verification workflow for Trusted and Assured Microelectronics
Formal Verification Feb 06, 2024 John Hallman pdf

January 2024

Welcome to the Enhanced Verification Academy 2.0 Forums!
Planning, Measurement and Analysis Jan 30, 2024 Dave Rich link
Comprehensive PCIe Verification Solution for Bleeding Edge and Mission Critical SoC & IP Designs
Verification IP Jan 24, 2024 Luis Rodriguez pdf
Comprehensive PCIe Verification Solution for Bleeding Edge and Mission Critical SoC & IP Designs
Verification IP Jan 24, 2024 Luis Rodriguez Webinar

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Functional Safety Webinar

Wednesday, Jan 29th-8:00 AM PST

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

Browse all content in Siemens Verification Academy with the tag execution semantics and synchronization

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