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June 2017 - Volume 13 Issue 2 (2)

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Show Less

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osmosis 2023
Formal Verification Nov 16, 2023 Nicolae Tusinschi Conference
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Debug Nov 09, 2023 Rich Edelman Webinar

October 2023

Smart Verification, Faster is not enough!
Machine Learning Oct 30, 2023 Harry Foster pdf
Verify designs created in MATLAB or Simulink within subsystem or full-chip UVM simulations
UVM Framework Oct 30, 2023 Bob Oden pdf
When it Comes to Artificial Intelligence and Machine Learning, Siemens Has You Covered
Machine Learning Oct 30, 2023 Tom Fitzpatrick pdf
Industry Trends in Functional Verification!
Planning, Measurement and Analysis Oct 30, 2023 Harry Foster pdf
Success with Continuous Integration and Continuous Development (CI/CD) Pipeline using automated checking
Questa Design Solutions Oct 30, 2023 Afzal Usmani - Siemens Eda pdf
MARLUG - 2023
Machine Learning Oct 30, 2023 Harry Foster Seminar
Selective hardening in space applications
Functional Safety Oct 24, 2023 Jacob Wiltgen link
Starting Your UVM Simulation
UVM - Universal Verification Methodology Oct 10, 2023 Chris Spear link
Selective Radiation Mitigation for Integrated Circuits
Functional Safety Oct 09, 2023 Jacob Wiltgen Paper
Selective Radiation Mitigation for Integrated Circuits
Functional Safety Oct 09, 2023 Jacob Wiltgen pdf
Questa Formal Apps Fact Sheet
Formal Verification Oct 01, 2023 link
Questa Verification IQ Fact Sheet
Verification IQ Oct 01, 2023 pdf
Questa RDC Fact Sheet
Reset-Domain Crossing Oct 01, 2023 pdf
Questa Lint Fact Sheet
Questa Design Solutions Oct 01, 2023 pdf
Austemper Analysis and Fault Simulation
Functional Safety Oct 01, 2023 pdf
QuestaSim Fact Sheet
Simulation Oct 01, 2023 pdf

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

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Upcoming FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Upcoming Formal Security Webinar

Wednesday, Feb 05th-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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November 2023

Combined formal and functional verification approach for digitally controlled analog frontend

Limits of verification: learnings from catastrophic system failures

How formal methods could banish the ghosts that haunt our computing systems

Prof. Wolfgang Kunz - RPTU & Tobias Ludwig - Lubis EDA

Hierarchical verification flow for FPGA design projects

How to sign-off cryptographic hash implementations with generated formal assertions

Debugging enhancements for formal property checking

osmosis 2023

Prevent Performance Problems with Prompt RTL Profiling

October 2023

Smart Verification, Faster is not enough!

Verify designs created in MATLAB or Simulink within subsystem or full-chip UVM simulations

When it Comes to Artificial Intelligence and Machine Learning, Siemens Has You Covered

Industry Trends in Functional Verification!

Success with Continuous Integration and Continuous Development (CI/CD) Pipeline using automated checking

MARLUG - 2023

Selective hardening in space applications

Starting Your UVM Simulation

Selective Radiation Mitigation for Integrated Circuits

Selective Radiation Mitigation for Integrated Circuits

Questa Formal Apps Fact Sheet

Questa Verification IQ Fact Sheet

Questa RDC Fact Sheet

Questa Lint Fact Sheet

Austemper Analysis and Fault Simulation

QuestaSim Fact Sheet