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July 2018

DAC 2018 Academy PDF Presentation: Portable Stimulus versus UVM: What's the Difference?
Standards Jul 30, 2018 pdf
Data Mining for SoC Level Performance
Planning, Measurement and Analysis Jul 26, 2018 Mark Olen pdf
Validating Your SoC is True to Requirements
Planning, Measurement and Analysis Jul 26, 2018 Stephen Bailey pdf
DAC 2018 Academy PDF Presentation: UVM 1800.2 & The New and Improved UVM Cookbook
Standards Jul 26, 2018 pdf
DAC 2018 Academy PDF Presentation: Portable Stimulus: A New Hope
Standards Jul 26, 2018 pdf
Building An Integrated Verification Flow
Planning, Measurement and Analysis Jul 26, 2018 Neil Johnson pdf
Emulation Platform Brings Unique Solutions to Automotive Market
Acceleration Jul 26, 2018 Vijay Chobisa pdf
AMS Verification Methodology for GPUs in AI and Deep Learning Applications
Analog Mixed-Signal Jul 26, 2018 pdf
DAC 2018 Academy PDF Presentation: Portable Stimulus from IP to SoC - Achieve More Verification
Standards Jul 26, 2018 pdf
DAC 2018 Academy PDF Presentation: Virtual Method Upcasting & Downcasting And Their Use In UVM
Standards Jul 26, 2018 pdf
No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!
Questa Design Solutions Jul 26, 2018 Kurt Takara mp4

June 2018

Comprehensive CDC Verification with Advanced Hierarchical Data Models
Clock-Domain Crossing Jun 29, 2018 Ping Yeung Article
Creating SoC Integration Tests with Portable Stimulus and UVM Register Models
Standards Jun 29, 2018 Matthew Ballance Article
It’s Not My Fault! How to Run a Better Fault Campaign Using Formal
Functional Safety Jun 29, 2018 Doug Smith Article
Coverage Driven Verification of NVMe Using Questa VIP (QVIP)
Verification IP Jun 29, 2018 Anurag Singh - Siemens Eda Article
Part 2: Power Aware Static Verification – From Power Intent to Microarchitectural Checks of Low-Power Designs
Low Power Jun 29, 2018 Progyna Khondkar Article
Three Main Components to Look for in Your Emulation Platform
Acceleration Jun 29, 2018 Vijay Chobisa Article
Complex Addressable Registers in Mission Critical Applications
Simulation Jun 29, 2018 Ishanee Bajpai - Agnisys Article
RTL Glitch Verification
Questa Design Solutions Jun 29, 2018 Ajay Daga - Fishtail Design Automation Article
UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer
Acceleration Jun 29, 2018 Marcela Zachariášová, Luboš Moravec - Codasip Ltd. Article

May 2018

What is Formal, and How It Works Under-the-Hood
Formal Verification May 14, 2018 Doug Smith Track
Instant Formal Expert
Formal Verification May 14, 2018 Dr. Jeremy Levitt Session
What is Formal, Anyway
Formal Verification May 14, 2018 pdf
Instant Formal Expert
Formal Verification May 14, 2018 pdf
What is Formal, Anyway?
Formal Verification May 14, 2018 Doug Smith Session

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Functional Safety Webinar

Wednesday, Jan 29th-8:00 AM PST

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Regression Webinar

Wednesday, Feb 12th-8:00 AM PST

Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Formal Security Webinar

Wednesday, Jan 22nd-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

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