About the UVM category
|
|
0
|
318
|
January 1, 2023
|
How can we verify a memory whose address location is swapped
|
|
19
|
10693
|
May 5, 2024
|
Uvm_sequencer usage
|
|
2
|
16
|
May 5, 2024
|
Seq_item_port driver-sequencer - communication issue
|
|
2
|
16
|
May 5, 2024
|
UVM Monitor the interface output, don't use the driver transaction - understanding this training recommendation
|
|
2
|
140
|
May 4, 2024
|
While i am using backdoor access for memory model i am able to writing the data into memory while reading the data from back door throug uvm ral i am getting error as either path is invalid or you dont have PLI/ACC visibility for that object
|
|
1
|
18
|
May 4, 2024
|
Overriding UVM_NONE messages
|
|
4
|
19
|
May 4, 2024
|
Coverage collector or subscriber usage
|
|
0
|
12
|
May 4, 2024
|
Overriding a parameter
|
|
9
|
14742
|
May 1, 2024
|
Uvm sequence body does not start after completion of base sequence pre_body
|
|
3
|
30
|
May 1, 2024
|
Uvm_reg_data_t constraint randomization
|
|
2
|
34
|
May 1, 2024
|
Analysis Port Write functionality
|
|
1
|
23
|
April 30, 2024
|
How to cover unsigned int
|
|
1
|
42
|
April 30, 2024
|
Clarifications about uvm_config db performance
|
|
3
|
58
|
April 26, 2024
|
How to set the config_db multiple times?
|
|
8
|
4698
|
April 26, 2024
|
Can we use tlm ports if so many componemts are there in sequence ordered defined like
|
|
3
|
38
|
April 25, 2024
|
What could be the reason for infinite loop in our code when dealing with sequence and driver
|
|
1
|
34
|
April 24, 2024
|
Register mirrored value should update until an event happens in temporal domain
|
|
1
|
28
|
April 25, 2024
|
Whether to use TLM ports or class object set in the uvm_config_db
|
|
4
|
40
|
April 24, 2024
|
Hierarchical uvm_reg_block add hdl path
|
|
0
|
31
|
April 24, 2024
|
Basic rule to use assertion in UVM
|
|
1
|
45
|
April 23, 2024
|
Skipping a register field from comparison with RAL
|
|
5
|
60
|
April 23, 2024
|
Uvm_hdl_read using macro for string path
|
|
1
|
25
|
April 22, 2024
|
If virtual sequencer contain a source sequencer and and destination sequencer and in test I am calling seq.start(envh.v_seqrh) then how ill the tool know to start the sequences on source sequencer or destination sequencer
|
|
2
|
42
|
April 22, 2024
|
Using uvm_config_db to register binded interfaces
|
|
4
|
54
|
April 21, 2024
|
Confusing UVM_ERROR in uvm_reg_bit_bash_seq
|
|
4
|
1928
|
April 19, 2024
|
How to create array of agent in environment with UVMF yaml
|
|
1
|
95
|
April 19, 2024
|
A better way of getting response back to a waiting sequence?
|
|
2
|
63
|
April 18, 2024
|
** Error: /vobs/ss_restart_vseq.sv(714): 'pass_ssr_vseq' is not a task name
|
|
3
|
41
|
April 18, 2024
|
How to manage compare policies if uvm_comparer should be avoided?
|
|
0
|
41
|
April 17, 2024
|