Released on September 21st, 2022.
Emerging 2.5D and 3DIC packaging technologies enable more design complexity, and bring some new verification challenges. We look at how to scale your verification capability to match and how to plan ahead for verification of die-to-die interconnect protocols such as UCIe and memory verification with HBM.
Packaging technologies for 2.5D and 3DIC are becoming more available and more accessible, with solutions addressing both the economics problem and the technical scalability challenge of building ever more complex SoCs. Standards are competing and emerging for interconnect protocols, memory interfaces, backplane-like and motherboard-like solutions within the IC package.
In this session, we take a look at how to scale your verification capability to match those designs, divide and conquer, and use the right abstractions to equip projects with high quality and faster time-to-market, and to equip design/verification engineers with scalable tools and solutions for verification. We will dive into the interface and memory protocols driving High Performance Compute innovation – PCIe Gen6, CXL, HBM3, and future UCIe, as well as important aspects of enabling scalability such as IDE security.
What You Will Learn:
- The challenges of verifying today’s advanced die-to-die interface and memory protocols
- The broad portfolio of Siemens EDA Verification IP solutions available today
- How our automated approach and flexible VIP can enable your productivity