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Questa Visualizer - Power Aware Debug
Demo - Mar 18, 2016 by Chuck Seeley
In this demo, you will learn the UPF based Power Aware Debug features available in Visualizer with Questa PASim.
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Introducing the Verification Academy Patterns Library!
Resource (Verification Horizons Blog) - Mar 16, 2016 by Harry Foster
If you have been involved in either software or advanced verification for any length of time, then you probably have heard the term Design Patterns . In fact, the literature for many of today’s testbench verification methodologies (such as UVM) often reference various software or object-oriented related patterns in their discussions.
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Walking
Resource (Pattern) - Mar 16, 2016 by Harry Foster
The walking pattern will be applicable for anyone focused on integration verification to effectively verify connectivity between various modules such as Address and Data bus. These are very commonly patterns used in stimulus and verification of RAM address and bus connectivity.
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Strategy
Resource (Pattern) - Mar 16, 2016 by Harry Foster
This pattern helps implement one of the basic principles of Object Oriented programming and defines a family of algorithms, encapsulate each one, and make them interchangeable. Strategy lets the algorithm vary independently from clients that use it.
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Certus™ Silicon Debug: Don’t Prototype Without It
Article - Mar 07, 2016 by Verification Horizons
FPGA PROTOTYPE RUNNING—NOW WHAT? Well done team; we've managed to get 100's of millions of gates of FPGA-hostile RTL running at 10MHz split across a dozen FPGAs. Now what? The first SoC silicon arrives in a few months so let's get going with integrating our software with the hardware, and testing the heck out of it. For that, we'll need to really understand what's going on inside all those FPGAs. Ah, there's the rub.
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Reusable Verification Framework
Article - Mar 03, 2016 by Verification Horizons
Testbenches written in SystemVerilog and UVM face the problem of configurability and reusability between block- and system-level. Whereas reuse of UVCs from a block- to a system-level verification environment is relatively easy, the same cannot be said for the UVC's connection to the harness: The interfaces that these UVCs need changes from connections to primary inputs and outputs at block level to a set of hierarchical probes into the DUT at system level. This requires a re-write of all interface connections and hinders reuse.
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Simplified UVM for FPGA Reliability: UVM for “Sufficient Elemental Analysis” in DO-254 Flows
Article - Mar 02, 2016 by Verification Horizons
DO-254 and other safety critical applications require meticulous initial requirements capture followed by accurate functional verification. “Elemental Analysis” in DO-254 refers to the verification completeness to ensure that all ‘elements’ of a design are actually exercised in the pre-planned testing. Code Coverage is good for checking if implementation code has been tested, but cannot guarantee functional accuracy. Currently, functional accuracy is guaranteed using pre-planned directed tests, auditing the test code and auditing the log files. This is not scalable as designs get complex. In this article we will look at using SystemVerilog syntax to concisely describe the functional coverage in the context of accurate “elemental analysis”.
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A Good Plan, Plus Automation, Plus the Right Tools, Equals...Useful.
Article - Mar 02, 2016 by Tom Fitzpatrick
Last spring, my wife and I decided to take a family vacation to Hawaii this February, which coincidentally is just before DVCon. We're celebrating several family milestones, including our 20th anniversary, my son's 18th birthday and my father-in-law's 80th, so we're all going. As I've mentioned before, my wife is great at planning and managing things like this, and there are many similarities between planning a vacation and managing a verification project. As we know, having a plan is critical to a project's success, so my endearingly "old-school" wife has all of our plans written out in a document, which she'll print out and bring with us. As a "tool guy," I showed her an app I use that will automatically load all our confirmation emails into a cool interactive itinerary. It's great to have a plan, but automation and tools are what make the plan into something usable. You'll see this theme throughout the following articles.
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DO-254 Compliant UVM VIP Development
Article - Mar 02, 2016 by Verification Horizons
Late 2014, we found ourselves in a Project to develop a custom interconnect UVM Compliant VIP. Not only was there a need to develop a custom UVM VIP, but there was a need to plug this to a DUT which has a PCIe and an Avalon Streaming interface on it and perform the advance verification using our custom UVM VIP.
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Simplifying Generation of DO-254 Compliant Verification Documents for AEH Devices
Article - Mar 02, 2016 by Verification Horizons
As per the DO-254 standard, the Airborne Electronic Hardware (AEH) needs accurate assurance of device behavior as intended within optimal operating conditions. For DAL A (Design Assurance Level A) Devices, you need to verify 100% functionality of the device and achieve 100% code coverage, including FEC. Code coverage can be managed using a simulation tool such as Questa®, while functional coverage would require a comprehensive Verification Case Document (VCD) that has cases traced to each requirement of the AEH device.
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Complex Signal Processing Verification under DO-254 Constraints
Article - Mar 02, 2016 by Verification Horizons
Building a complex signal processing function requires a deep understanding of the signal characteristics and of the different algorithms and their performances. When it comes to the verification (a) of such designs, a quite generic approach consists of injecting more or less realistic stimulus and using reference models (most often C or Matlab ® ), to compare the expected results. Requirement based designs following a DO-254 (1) process add the constraints that each function of the design should be specified as a traceable requirement. The proof of the complete verification of each requirement should also be provided with additional emphasis on physical verification, therefore running the tests on the physical device.
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Nine Effective Features of NVMe® Questa® Verification IP to Help You Verify PCIe® Based SSD Storage
Article - Mar 02, 2016 by Verification Horizons
Non-Volatile Memory Express ® (NVMe ® ) is a new software interface optimized for PCIe ® Solid State Drives (SSD). It significantly improves both random and sequential performance by reducing latency, enabling high levels of parallelism, and streamlining the command set while providing support for security, end-to-end data protection, and other client and enterprise features. NVMe provides a standards-based approach, enabling broad ecosystem adoption and PCIe SSD interoperability.
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Verifying Display Standards: A Comprehensive UVM-based Verification IP Solution
Article - Mar 02, 2016 by Saumya Agrawal
The display protocol IP market is growing at a very fast pace. This is chiefly the outcome of the incredible increase in popularity of a wide variety of display source devices: such as DVD players, computer systems, and display sink/receiver devices: such as televisions, projectors, and display instruments. End users, the consumers, have also become more technologically savvy, increasing the demand for more and better products.
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Total Recall: What to Look for in a Memory Model Library
Article - Mar 02, 2016 by Mark Peryer
Almost all electronics systems use memory components, either for storing executable software or for storing data. Accurate memory models are fundamental. Making these models available in proven, standards-based libraries is essential to functional verification of these kinds of designs. The models that make up the library should possess specific qualities, and the library itself should deliver a comprehensive solution that supports any type of simulation environment.
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MIPI C-PHY™: Man of the Hour
Article - Mar 02, 2016 by Verification Horizons
The MIPI Alliance signature dishes, C-PHY™ and D-PHY™, are becoming favorite dishes of the imaging industry. These interfaces allow system designers to easily scale up the existing MIPI Alliance Camera Serial Interface (CSI-2™) and Display Serial Interface (DSI™) ecosystems to support higher resolution image sensors and displays while keeping low power consumption at the same time. This gives them an edge to get more into the mobile systems with bigger and better pictures.
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The Verification Academy Patterns Library
Article - Mar 02, 2016 by Harry Foster
The literature for many of today’s testbench verification methodologies (such as UVM) often reference various software or object-oriented related patterns in their discussions. For example, the UVM Cookbook (available out on the Verification Academy) references the observe pattern when discussing the Analysis Port.
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First Time Unit Testing Experience Report with SVUnit
Article - Mar 02, 2016 by Neil Johnson
Verification teams don’t typically verify testbench components. But this Qualcomm Technologies IP team realized the necessity of unit testing a critical testbench component and the corresponding debug time and frustration it could prevent for downstream IP and chip teams.
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An Evaluation of the Advantages of Moving from a VHDL to a UVM Testbench
Article - Mar 02, 2016 by Verification Horizons
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QVM: Enabling Organized, Predictable, and Faster Verification Closure
Article - Mar 02, 2016 by Verification Horizons
Until recently, the semiconductor industry religiously followed Moore's Law by doubling the number of transistors on a given die approximately every two years. This predictable growth allowed ecosystem partners to plan and deal with rising demands on tools, flows and methodologies. Then came the mobile revolution, which opened up new markets and further shifted the industry's focus to consumers.
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Increased Efficiency with Questa VRM and Jenkins Continuous Integration
Article - Mar 01, 2016 by Thomas Ellis
For all the incredible technological advances to date, no one has found a way to generate additional time. Consequently, there never seems to be enough of it. Since time cannot be created, it is utterly important to ensure that it is spent as wisely as possible.
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Software-Driven Testing of AXI Bus in a Dual Core ARM® System
Article - Feb 29, 2016 by Mark Olen
Here we present an architecture for verifying proper operation and performance of a complex AXI bus fabric in a dual-core ARM® processor system using a combination of SystemVerilog and C software-driven test techniques. Specifically, we describe deployment of an advanced graph-based solution that provides the capability for checking full protocol compliance, an engine for continuous traffic generation, precise control and configurability for shaping the form and type of traffic needed to test the fabric. These characteristics were easier to construct, easier to analyze and review, and were more efficient in terms of achieving coverage using a graph-based approach than constrained-random or directed OVM sequences. For us, this architecture yielded successful completion of the verification process ahead of schedule.
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Whose Fault is It? Advanced Techniques for Optimizing ISO 26262 Fault Analysis
Paper - Feb 28, 2016 by Avidan Efody
This paper deals with transient fault analysis towards ISO 26262 certification. First we suggest a way to estimate ISO 26262 required metrics with a user specified level of accuracy using statistical sampling of transient faults. We then propose a technique that reuses existing regression results in order to minimize the resources required to analyze faults in both combinatorial and sequential elements.
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Whose Fault is It? Advanced Techniques for Optimizing ISO 26262 Fault Analysis
Resource (Technical Paper) - Feb 28, 2016 by Avidan Efody
Abstract-Shrinking nodes and reduced supply voltages make transient faults due to electromagnetic interferences a growing concern for mission critical ASICs and FPGAs. To address this risk, the ISO 26262 safety automotive standard requires that the impacts of transient faults on safety goals are rigorously analyzed[1]. Such analysis is far from trivial, first and foremost due to the practically infinite number of fault and state combinations that could happen in a component’s life cycle.
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The Downside of Advanced Verification
Session - Feb 22, 2016 by Neil Johnson
After more than a decade, it’s become obvious the advanced verification techniques we rely on, like constrained random verification, have fallen short of their potential.
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Introduction to SVUnit
Session - Feb 22, 2016 by Neil Johnson
A history of SVUnit and how it helps to directly address the poor code quality and code debug (redo) currently plaguing semiconductor teams.