- Rich Edelman - Mentor Graphics
SystemVerilog is a powerful language which can be used to build models of RTL in order to facilitate early testbench testing. The early RTL model uses higher level abstractions like SystemVerilog threads, queues, dynamic arrays and associative arrays. Using high level abstractions allows a functional model to be created with little effort. A simple fabric model is created implementing AXI-like READY/VALID channels.
Building a UVM  testbench is a hard job, made harder when operational RTL is not yet available to test. SystemVerilog  is a powerful modeling language that can be used to build a high level model of hardware before RTL is available. This model is fast to write, and can be as functionally complete as needed. This paper will describe the creation and use of a fabric model to build and bring up a testbench. When the RTL is available it can be plugged into the testbench model with little change required.
The main contributions of this paper are: showing a fully functional model of a medium complexity communication fabric; writing the model using SystemVerilog; and building a reusable testbench that can support block testing as well as support system level tests. The testbench implementation is not discussed in this paper. Contact the author for more information.
The fabric is a simple two port switch with buffering. Each communication pathway contains 5 channels. Each channel is a Ready/Valid channel with similarities to an AMBA® AXI™  channel. The fabric supports multiple outstanding transactions, pipelining and large burst data transfers. It also supports traffic priority (quality of service). This is the model. It is written using SystemVerilog. Associative arrays are used to manage out-of-order transactions. Queues and dynamic arrays are used for managing lists. Classes are used to hold the transferred information - a class each for RA (Read Address), WA (Write Address), RD (Read Data), WD (Write Data) and B (Write Response), respectively. Packed structs are used for managing the tag bit fields.
The testbench is built to test the features supported by the fabric. It is a basic block testbench, testing transfer, buffering limits and other edge conditions in the RTL. This testbench will also be reusable to the system tests. The testbench is a basic UVM testbench with transfer sequences and background traffic sequences available.
The actual device under test will be two fabrics connected together, as in Figure 2.
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Read the entire No RTL Yet? No Problem UVM Testing a SystemVerilog Fabric Model technical paper.
DVCon US 2016