Verification Academy

Topic	Replies	Views	Activity
Bitwise toggle coverage for a bitvector SystemVerilog SystemVerilog	31	39417	May 10, 2020
Bit slicing in systemVerilog SystemVerilog SystemVerilog	12	80972	January 4, 2019
What is the difference between @(posedge clk) begin end.... and @(posedge clk);? SystemVerilog SystemVerilog , Race-condition , posedge , posedge-clk , posedge-clk-begin	15	68630	November 16, 2018
How to force dut internal signals in UVM environment UVM UVM	11	65401	September 30, 2020
Confusion over casting of classes SystemVerilog SystemVerilog	14	56252	October 25, 2018
Importance of the clone( ) method OVM OVM	17	45225	September 25, 2021
About type_id::create() OVM OVM	14	48235	January 24, 2020
SystemVerilog $feof() SystemVerilog SystemVerilog	18	42083	October 29, 2019
What is the difference between uvm_config_db and uvm_resource_db? UVM UVM , uvm_config	17	42312	July 23, 2024
Difference Between UVM_OBJECT and UVM_COMPONENT UVM UVM , UVM_OBJECT-and-UVM_COMPONENT	13	47293	January 15, 2018
Usage of Var SystemVerilog SystemVerilog , reg-wire-logic	11	26817	March 15, 2023
Calling randomize() from a sequence OVM OVM	19	34249	July 1, 2009
How to define cross coverage for the selected range SystemVerilog SystemVerilog	12	39742	March 10, 2017
How do I connect inout ports? SystemVerilog SystemVerilog , Inout-port	10	39555	May 16, 2021
Generate block in SV SystemVerilog SystemVerilog	9	38018	December 19, 2016
OVM wrapper for Verilog Bfms? OVM OVM	26	22900	February 27, 2019
How to define a condition for a covergroup (using iff)? SystemVerilog SystemVerilog	17	28001	November 7, 2021
Do you `include or import? OVM OVM	11	34150	July 13, 2010
How to manage the seed of randomization? OVM OVM	9	34431	March 15, 2019
Calling of build phase? UVM UVM , UVM_PHASE , build_phase	26	20104	November 14, 2024
Uvm_component_utils with parameters UVM UVM	13	27816	January 24, 2020
USING std::randomize functio SystemVerilog SystemVerilog	12	28354	October 31, 2014
Virtual interface resolution cannot find a matching instance of interface OVM OVM	21	21740	November 21, 2016
How does forever behaves in fork block SystemVerilog SystemVerilog	13	26592	October 2, 2020
Randomizing the prime numbers SystemVerilog SystemVerilog , array-randomization , constraint-foreach-loop , prime-number-constraint	10	16768	June 26, 2024
Assertion to check for the toggle (0->1) of a signal SystemVerilog SystemVerilog , Assertion-for-toggle-coverage	11	16033	November 15, 2019
Always block in task SystemVerilog SystemVerilog	17	23141	February 27, 2024
Accessing a generate block hierarchy SystemVerilog SystemVerilog	12	26561	August 31, 2016
Vim Syntax highlighting for SystemVerilog and OVM OVM OVM	11	27195	March 4, 2011
How can I assign one interface to another interface without manually connecting all signals? SystemVerilog SystemVerilog , Interfaces	11	15075	August 30, 2022
Function new() overriding ? why should we call super.new() function in derived class constructor? SystemVerilog SystemVerilog	13	24463	July 13, 2018
Distributed weightage constraint SystemVerilog SystemVerilog	9	28817	January 19, 2021
The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it UVM UVM , UVM-SystemVerilog	38	14497	November 30, 2021
Hierarchial access for DUT signals OVM OVM	15	22066	November 29, 2016
Out of order in driver and scoreboard UVM UVM , uvm_driver , uvm_scoreboard	11	25207	October 15, 2019
UVM Test is not comming out UVM UVM	17	19631	July 9, 2016
Please format your code with markdown or <code> </code> tags Announcements Announcements	9	25194	August 8, 2024
" uvm_do_on_with " constraint issue UVM UVM	9	25063	August 8, 2020
OVM Verbosity OVM OVM	13	20841	August 27, 2009
SVA: Package for dynamic and range delays and repeats SystemVerilog SystemVerilog , dynamic-delays-dynamic-repeats	10	23506	May 7, 2024
Array sum() method issue SystemVerilog SystemVerilog	11	21818	July 14, 2021
UVM Register Kit for OVM 2.1.2 Downloads UVM , Downloads , registers	20	16211	May 4, 2012
Global_stop_request() & $finish OVM OVM	17	17446	June 19, 2009
Using 'ref' with variables in interface SystemVerilog SystemVerilog	14	18690	April 11, 2019
How to use tlm_analysis_fifo? UVM UVM	14	18591	July 17, 2024
Method/function overloading SystemVerilog SystemVerilog	15	17869	November 7, 2024
Array of cover points in a covergroup Coverage Coverage , functional-coverage	12	19672	July 14, 2021
Set_type_override_by_type OVM OVM	9	22315	April 7, 2017
Assigning elements of an virtual interface array? OVM OVM	14	18092	May 8, 2008
Getting error as unexpected identifier and error in class specification UVM UVM	17	16441	May 13, 2016