Getting error as unexpected identifier and error in class specification

UVM
1

HI all,

I am new to uvm,

I am running adder block in uvm .Getting some errors. Any help for these unexpected identifier and error in class extension

  • Error: …/tb/sequence.svh(1): near “uvm_sequence”: syntax error, unexpected IDENTIFIER
    ** Error: …/tb/sequence.svh(1): Error in class extension specification.
    ** Error: …/tb/my_sequencer.svh(1): near “#”: syntax error, unexpected ‘#’, expecting class
    ** Error: …/tb/driver.svh(1): near “uvm_driver”: syntax error, unexpected IDENTIFIER
    ** Error: …/tb/driver.svh(1): Error in class extension specification.
    ** Error: …/tb/agent.svh(1): near “#”: syntax error, unexpected ‘#’, expecting class
    ** Error: …/tb/env.svh(1): near “uvm_env”: syntax error, unexpected IDENTIFIER
    ** Error: …/tb/env.svh(1): Error in class extension specification.
    ** Error: …/tb/test.svh(1): near “uvm_test”: syntax error, unexpected IDENTIFIER
    ** Error: …/tb/test.svh(1): Error in class extension specification.
    ** Error: …/tb/driver.svh(1): near “(”: syntax error, unexpected ‘(’, expecting class
    End time: 17:04:58 on Jun 23,2015, Elapsed time: 0:00:02
2

In reply to dileep254:

Can you provide the code for the above file

3

In reply to jatin.rathod:

HI jatin

1)This is my adder block in system verilog counter_2.sv
module counter_2(input A,B,
output SU,C);
assign {C,SU}=A+B;
endmodule

  1. This is interface created interf.svh

interface intf();
logic A,B;
logic SU,C;
endinterface

4

In reply to dileep254:

HI jatin,

This is my env code created in env.svh

class my_env extends uvm_env;

`uvm_component_utils(my_env)

my_agent agg;

function new(string name,uvm_component parent);
super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);
agg=agent::type_id::create(“agg”,this);
endfucntion

endclass:env

…

This is my test code created in test.svh

class my_test extends uvm_test;

`uvm_component_utils(agent)
virtual intf intf1();
my_env envy;
my_sequence seq;

//

function new(string name,uvm_component parent);
super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);
envy=env::type_id::create(“env”,this);
if(!uvm_config_db#(virtual intf)::get(this,“”,intf1,intf1))
begin
`uvm_info(“test”,“config not done”,UVM_LOW)
end
uvm_config_db#(virtual intf)::set(this,“envy.agg.drv”,intf1,intf1);
endfucntion

task run_phase(uvm_phase phase)
phase.raise_objection(this);
begin
#10;
`uvm_info(“kk”,“hello dileep”,UVM_LOW);
seq.start(envy.agg.sequencer);
end
phase.drop_objection(this);
endtask

endclass
…

This is my top module …

module top;
import uvm_pkg::*;
intf intf1();
counter_2 dkk(.A(intf1.A),.B(intf1.B),.Su(intf1.su),.C(intf1.C));
initial
begin
uvm_config_db#(virtual intf)::set(null,“uvm_test_top”,intf1,intf1);
run_test(my_test);
end
endmodule

5

In reply to dileep254:

This is my sequencer component created in my_sequencer.svh

class my_sequencer extends uvm_sequencer#(trasaction);
`uvm_component_utils(my_sequencer)

function new(string name=“”,uvm_component parent);
super.new(name,parent);
endfucntion

endclass

…

THis is my agent component created in agent.svh

class my_agent extends uvm_agent;

`uvm_component_utils(my_agent)

my_driver drv;
my_sequencer sequencer;

function new(string name,uvm_component parent);
super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);
drv=driver::type_id::create(“driver”,this);
sequencer=my_sequencer::type_id_create("sequencer);
endfucntion

function void connect_phase(uvm_phase phase);
drv.seq_item_port.connect(sequencer.item_export);
endfunction

endclass

…

6

In reply to dileep254:

This is my sequence componnet code created in sequence.svh

class my_sequence extends uvm_sequence#(trasaction);
`uvm_object_utils(my_sequence)
function new(string name=“”);
super.new(name);
endfunction

task body;
repeat(1)
begin
reqe=transaction::type_id::create(“reqe”);
start_item(reqe);
assert(reqe.randomize());
finish_item(reqe);
end
endtask
endclass
…
This is my sequence item code created in trasaction.svh

import uvm_pkg::*;
class transaction extends uvm_sequence_item;

rand bit A;
rand bit B;

uvm_object_utils_begin(transaction) uvm_field_int(A,UVM_ALL_ON)
uvm_field_int(B,UVM_ALL_ON) uvm_object_utils_end

function new(string name=“”);

super.new(name);

endfunction

endclass

…

7

In reply to dileep254:

This is my driver component created in driver.svh

class my_driver extends uvm_driver#(trasaction);

`uvm_component_utils(my_driver)
virtual intf intf1;
function new(string name,uvm_component parent);
super.new(name,parent);
endfunction

function void buid_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(virtual intf)::get(this,“”,“intf1”,intf1))
begin
`uvm_info(“kk”,“uvm_config_db::get failed”,UVM_LOW)
end
endfunction

task run_phase(uvm_phase phase);
forever
begin
trasaction req;
seq_item_port.get_next_item(req);
intf1.A=req.A;
intf1.B=req.B;
seq_item_port.item_done();
end
endtask

endclass

8

In reply to dileep254:

HI jatin

Above is the uvm code what i have run and created .f file and i run the command vlog -f filelist.f and got the baove errors

+incdir+ …/dut/counter_2.sv
+incdir+ …/tb/interf.svh
+incdir+ …/tb/testlist.svh
+incdir+ …/tb/trasaction.svh
+incdir+ …/tb/sequence.svh
+incdir+ …/tb/my_sequencer.svh
+incdir+ …/tb/driver.svh
+incdir+ …/tb/agent.svh
+incdir+ …/tb/env.svh
+incdir+ …/tb/test.svh
+incdir+ …/tb/toptest.sv

9

In reply to dileep254:

Hey,
I see that you have the following syntax my_sequence extends uvm_sequence#(trasaction). Is this intentional or is it a typo?(shouldn’t it have been transaction?)
Try this this and let us know if this goes away.
and make sure you are compiling uvm_macros.svh (required for automation macros) and uvm_dpi.cc files. ( required for command line processing etc.)

  • Sujith SH
10

In reply to sujithsh:

Hey sujith,

There was typo in Trasaction. But still i am getting the above errors.

Hey how to check the uvm_dpi.cc files for command lien processing

11

Are you importing the uvm_pkg? Are you including the uvm_macros.svh?

Show the top level packages that you are generating to compile your code and we can provide some more help.

12

In reply to cgales:

Hi

In my testlist.svh file i am importing uvm_pkg and uvm_macros.svh

`include “uvm_macros.svh”
import uvm_pkg::*;
IN filelist.f I included all files
+incdir+ …/dut/counter_2.sv …DUT file
+incdir+ …/tb/interf.svh …Interface signals
+incdir+ …/tb/testlist.svh … contains UVM_pkg and uvm_macros
+incdir+ …/tb/trasaction.svh …UVM_sequence_item
+incdir+ …/tb/sequence.svh … UVM_Sequence object
+incdir+ …/tb/my_sequencer.svh …UVM_Sequencer component
+incdir+ …/tb/driver.svh … UVM_driver component
+incdir+ …/tb/agent.svh …Agent component
+incdir+ …/tb/env.svh …environment component
+incdir+ …/tb/test.svh … Test component
+incdir+ …/tb/toptest.sv … top module which runs the test component

And I ran the command vlog -f filelist.f

13

In reply to dileep254:

Compiling files individually won’t work, as SystemVerilog considers each file a unique scope.

Please see https://blogs.sw.siemens.com/verificationhorizons/2010/07/13/package-import-versus-include/

14

In reply to cgales:

Change your compilation to put all classes in a package by creating a my_package.sv file that you put in your filelist.f

`include "uvm_macros.svh"
package my_package;
import uvm_pkg::*;
`include "testlist.svh" // ............. !!! remove UVM_pkg and uvm_macros
`include "trasaction.svh" // .............UVM_sequence_item
`include "sequence.svh" // .......... UVM_Sequence object
`include "my_sequencer.svh" // .............UVM_Sequencer component
`include "driver.svh" // ........... UVM_driver component
`include "agent.svh" // .............Agent component
`include "env.svh" // .........environment component
`include "test.svh" // ........ Test component
endpackage

Then add the following to your toptest.sv file

`include "uvm_macros.svh"
import uvm_pkg::*;
import my_package::*;
15

In reply to dave_59:

HI Dave ,

THanks a lot . Solved some errors.But still getting errors as below . where one error is[ Cannot find `include file “uvm_macros.svh” in directories:] because tool was selecting the [/tools/bda/questa/questasim/ovm-2.1.2/…/verilog_src/ovm-2.1.2/src] OVM path .I think so. How to change the path

vlog -f file.f -R +UVM_TESTNAME=my_test
QuestaSim vlog 10.3c Compiler 2014.07 Jul 18 2014
Start time: 15:35:25 on Jul 01,2015
vlog -f file.f -R “+UVM_TESTNAME=my_test”
– Compiling module counter_2
– Compiling interface intf
** Error: …/tb/pac.sv(1): Cannot find include file "uvm_macros.svh" in directories: , , , , /tools/bda/questa/questasim/ovm-2.1.2/../verilog_src/ovm-2.1.2/src -- Compiling package pac -- Importing package uvm_pkg (uvm-1.1d Built-in) ** Error: ** while parsing file included at ../tb/pac.sv(4) ** at my_transaction.svh(6): (vlog-2163) Macro uvm_object_utils_begin is undefined.
** Error: ** while parsing file included at …/tb/pac.sv(4)
** at my_transaction.svh(6): near “(”: syntax error, unexpected ‘(’, expecting function or task
** Error: ** while parsing file included at …/tb/pac.sv(4)
** at …/tb/toptest.sv(1): Cannot find `include file “uvm_macros.svh” in directories:
, , , , /tools/bda/questa/questasim/ovm-2.1.2/…/verilog_src/ovm-2.1.2/src
– Compiling module top
** Error: ** while parsing file included at …/tb/pac.sv(5)
** at sequence.svh(6): near “m”: syntax error, unexpected IDENTIFIER, expecting class
End time: 15:35:26 on Jul 01,2015, Elapsed time: 0:00:01
Errors: 5, Warnings: 0

16

In reply to dileep254:

There is no way that the tool should have tried to compile OVM code unless you accidentally had import ovm_pkg::* somewhere, or have messed up the default files. However this forum is not for tool specific help, you need to contact your vendor directly.

17

hello sir
I am new to UVM
I get this error

** Error: mem_transfer.sv(2): near “uvm_sequence_item”: syntax error, unexpected IDENTIFIER

** Error: mem_transfer.sv(2): Error in class extension specification.

** Error: uvm_sequences.sv(4): near “uvm_sequence”: syntax error, unexpected IDENTIFIER

** Error: uvm_sequences.sv(4): Error in class extension specification.

** Error: mem_if.sv(4): near “#”: syntax error, unexpected ‘#’, expecting class

** Error: mem_driver_rsp.sv(3): near “uvm_driver”: syntax error, unexpected IDENTIFIER

** Error: mem_driver_rsp.sv(3): Error in class extension specification.

** Error: mem_monitor.sv(3): near “#”: syntax error, unexpected ‘#’, expecting class

** Error: mem_env.sv(2): near “uvm_env”: syntax error, unexpected IDENTIFIER

** Error: mem_env.sv(2): Error in class extension specification.

** Error: uvm_sequences.sv(3): near “uvm_sequence”: syntax error, unexpected IDENTIFIER

** Error: uvm_sequences.sv(3): Error in class extension specification.

** Error: mem_test.sv(3): near “#”: syntax error, unexpected ‘#’, expecting class

** Error: C:/questasim_10.2c/win32/vlog failed.

18

In reply to Sharmela:

Did you read my response?