Topics tagged Verilog

Topic	Replies	Views	Activity
Why we need x and z values since our chip will work with only 0's and 1's? SystemVerilog SystemVerilog , Verilog , randomization , xz_values	4	1344	November 8, 2017
Connecting a DUT to different Verilog modules from within UVM UVM UVM , Verilog	3	3505	August 15, 2016
Advice on how to slice a dynamic array SystemVerilog SystemVerilog , Verilog , array-slicing	6	11102	March 8, 2016
Concurrent VS Sequential coding to speed up the simulation run time SystemVerilog SystemVerilog , Sequential-sequence , Verilog , simulation-profile , runtime-speed	1	1435	November 2, 2015
Running UVM example on MODELSIM - ALTERA 10.1d UVM UVM , System-Verilog , Verilog , modelsim , Altera	4	5225	March 18, 2015
Variable clock generation in verilog using task SystemVerilog SystemVerilog , Clock-generator , task , Verilog	0	9321	January 20, 2015
Mod 10 in Verlig SystemVerilog SystemVerilog , Verilog , synthesize	1	1874	December 15, 2014
Comparison of the advantages/disadvantages of using VHDL or Verilog for hardware verification SystemVerilog SystemVerilog , testbench-environment , functional-verification , VHDL , Verification , Verilog	11	12984	September 23, 2014