Concurrent VS Sequential coding to speed up the simulation run time

SystemVerilog
, , , ,
1

Hi,

Could you please let me know, if I write a particular logic using concurrent way or in sequential way , which will be execute faster/slower . ? Which has advantage over the other ?

Here we have 2 events

  1. Increment a counter
  2. Display the value of the counter.

Example code snippets for the requirements :

Code1:

fork 
forever (@posedge clk) begin
   if (en) begin
     count = count +1;
     display("new count value")
   end
end
join_none

VS:
Code2:

Now lets assume the count is incrementing in some other parallel block, to display the value of count we are using a parallel thread like below .

fork 
  forever@(posedge clk) begin
   if (en) begin
     count = count +1;
   end
 end
join_none

fork 
  forever @count
  display("new count value") 
join_none

Which among the 2 codes will make the simulator run faster ? if so why. Actual case I have is much more complex, but I just tried to illustrate my problem with this basic code.

Thanks

2

The first code example will probably execute faster because there is only one process and no overhead in communication between the two processes. But simulators have a lot of optimizations that could change the answer to your question depending on the actual code. It’s also hard to comment on the advantages of either style without seeing more code.