Topics tagged RAL

Topic	Replies	Views	Activity
Predicting Read Only Register in RAL UVM UVM , RAL , prediction-monitor-scoreboard , predictors	1	676	November 30, 2023
How to do Scoreboarding or checking the WR_data and read data matching in RAL UVM UVM , RAL	1	374	November 29, 2023
How to set a register to a value thru a hierarchy receiving as string? UVM UVM , RAL , accessing-the-associative-array-elements , systemverilog-Arrays	3	593	October 4, 2023
Environment and DUT random configuration UVM UVM , RAL , configuration , randomization , UVM-Environment	7	622	September 25, 2023
IN UVM RAL Adapter class, why do we use const ref for uvm_bus_reg_op in reg2bus and only ref for uvm_bus_reg_op in bus2reg? UVM UVM , RAL , adapter	1	316	August 25, 2023
Info regarding built in sequences for memory UVM UVM , RAL	6	673	May 23, 2023
What is the purpose of bus_req.end_event.wait_on(); in uvm_reg_map::do_bus_write UVM UVM , RAL	1	500	March 21, 2023
RAL: set_check_on_read(1) does not work with frontdoor access and passive prediction? UVM UVM , RAL , auto-prediction , set_check_on_read	0	624	March 9, 2023
DUPIDN compilation error for reg models UVM UVM , RAL , RAL-IPXACT , UVM-UVMRAL	0	350	February 27, 2023
UVM RAL sequences with priority UVM UVM , RAL , sequence-arbitration , sequencer-arbitration , UVM-RAL-SEQUENCE	4	844	February 15, 2023
Invalid Register access UVM UVM , RAL , uvm-register-model , -UVM-warnings-disable	4	838	February 6, 2023
How to get uvm_reg_file instance by name in uvm_reg_block UVM UVM , RAL , uvm_ral	0	422	January 9, 2023
Write '1' and '0' is not happening while running bit bash sequence UVM UVM , RAL , UVM-bit_bash	1	544	January 2, 2023
How to implement $sformatf on register models UVM UVM , assertion , RAL	6	738	December 21, 2022
Register Backdoor Issue UVM UVM , RAL , Cookbook-RegistersBackdoorAccess , UVM-RAL-Backdoor-Write-hdl_path	3	4065	November 4, 2022
How to find, if register model is updated or not UVM UVM , RAL	0	415	August 19, 2022
A resource with meta characters in the field name has been created "m_regmod " UVM UVM , RAL , uvm_ral	0	804	July 13, 2022
RAL read and auto_predict UVM UVM , RAL	0	585	May 4, 2022
Hanging register write UVM UVM , RAL , Write , hang , UVM_IS_OK	1	560	April 16, 2022
Combining all reg_models into one UVM UVM , RAL , systemverilog-uvm , UVM-RAL-UVM	3	1051	March 7, 2022
RAL read and write issues to Design UVM UVM , RAL , RAL-UVM	9	1471	March 7, 2022
Functions inside apb adapter are not being called from the test sequence UVM UVM , RAL , RAL-UVM , uvmral	2	761	February 23, 2022
What is difference between set_cfg and configure method in ral? OVM OVM , RAL	1	765	February 3, 2022
RAL mirror() method with UVM_CHECK not printing error messages UVM UVM , RAL , mirror , UVM_CHECK	0	841	October 26, 2021
$cast failed using parameterised uvm_sequence_item class UVM SystemVerilog , UVM , RAL , OOP	8	1857	October 14, 2021
How do you assign different sequencers to different reg_map? UVM UVM , RAL , uvm_reg_map	0	744	September 23, 2021
How do I get multiple transactions if register width is wider or narrower than bus width? UVM SystemVerilog , UVM , RAL	0	783	June 5, 2021
UVM_RAL: Why Predictor calling bus2reg function(Adapter) 2 times automatically? UVM UVM , RAL , Mirrored-values-and-desired-values-in-UVM-RAL	10	4644	February 19, 2020
Setting endianness for every uvm_reg UVM UVM , RAL	2	1515	April 9, 2019
RAL :: get_reg_by_offset() method UVM UVM , RAL , uvm-ral	4	6095	November 14, 2018