Topics tagged RAL

Topic	Replies	Views	Activity
How to Selectively skip STS ( RO ) registers in bit_bash UVM UVM , RAL , uvm_reg_bit_bash	0	115	September 19, 2024
How to check the register is implemented in UVM RAL with the address UVM UVM , RAL , uvm_reg	1	198	September 3, 2024
Testing of Read/Write register through RAL when bug is there UVM UVM , RAL	1	177	August 22, 2024
How to get Backdoor Access for Memory? UVM RAL	0	159	August 8, 2024
Proper reg_map has not picked up UVM RAL	5	166	July 4, 2024
UVM register model UVM RAL , uvm-ral	0	148	July 1, 2024
RAL Register access UVM RAL	3	379	May 16, 2024
Skipping a register field from comparison with RAL UVM RAL , uvm_ral , RAL-UVM	10	744	May 15, 2024
Macro to read register fields using RAL Coverage UVM , Coverage , assertion , RAL , System-Verilog	1	325	March 26, 2024
How to use get_full_hdl_path for the register UVM RAL	0	473	March 15, 2024
RAL Backdoor access, set hdl paths UVM UVM , RAL	1	323	February 29, 2024
Question related to RAL methods SystemVerilog UVM , RAL , uvm_ral , RAL-UVM	0	308	February 26, 2024
How to access UVM_MEM using the .write method UVM UVM , RAL , uvm_mem	2	491	February 25, 2024
UVM RAL Memory - Sampling after read/write operation UVM SystemVerilog , Coverage , RAL , uvm_mem , Sampling	0	536	February 3, 2024
My question is how to verify “R0” (Read only) registers through backdoor or front door mechanism ? In frontdoor usually we do masking of RO registers to not to write .If RO register is designed with bug with RW type how to verify this issue without write UVM RAL	1	374	January 23, 2024
In UVM RAL, I have 2 active agentS,only one adaptor. how to work 2 transaction in one adaptor? UVM UVM , RAL , RAL-register-UVM , uvm-ral , UVM-RAL-systemverilog-ralmodelling , RAL-UVM	0	314	December 29, 2023
Access (to W/R) 2 Specific fields in a 32-bit register UVM RAL , uvm-ral , Systemverilog-UVM-RAL	1	330	December 27, 2023
RAL Integration UVM UVM , RAL , APB , vip-intergrate , register_model	0	408	December 11, 2023
I had an issue regarding RAL, i am unable to create a map which should contains maps of different invidual registers UVM UVM , RAL , RAL-UVM	0	321	December 6, 2023
Predicting Read Only Register in RAL UVM UVM , RAL , prediction-monitor-scoreboard , predictors	1	840	November 30, 2023
How to do Scoreboarding or checking the WR_data and read data matching in RAL UVM UVM , RAL	1	428	November 29, 2023
How to set a register to a value thru a hierarchy receiving as string? UVM UVM , RAL , accessing-the-associative-array-elements , systemverilog-Arrays	3	686	October 4, 2023
Environment and DUT random configuration UVM UVM , RAL , configuration , randomization , UVM-Environment	7	661	September 25, 2023
IN UVM RAL Adapter class, why do we use const ref for uvm_bus_reg_op in reg2bus and only ref for uvm_bus_reg_op in bus2reg? UVM UVM , RAL , adapter	1	330	August 25, 2023
Info regarding built in sequences for memory UVM UVM , RAL	6	706	May 23, 2023
What is the purpose of bus_req.end_event.wait_on(); in uvm_reg_map::do_bus_write UVM UVM , RAL	1	538	March 21, 2023
RAL: set_check_on_read(1) does not work with frontdoor access and passive prediction? UVM UVM , RAL , auto-prediction , set_check_on_read	0	704	March 9, 2023
DUPIDN compilation error for reg models UVM UVM , RAL , RAL-IPXACT , UVM-UVMRAL	0	357	February 27, 2023
UVM RAL sequences with priority UVM UVM , RAL , sequence-arbitration , sequencer-arbitration , UVM-RAL-SEQUENCE	4	935	February 15, 2023
Invalid Register access UVM UVM , RAL , uvm-register-model , -UVM-warnings-disable	4	905	February 6, 2023

How to Selectively skip STS ( RO ) registers in bit_bash

UVM

UVM , RAL , uvm_reg_bit_bash

0

115

September 19, 2024

How to check the register is implemented in UVM RAL with the address

UVM

UVM , RAL , uvm_reg

1

198

September 3, 2024

Testing of Read/Write register through RAL when bug is there

UVM

UVM , RAL

1

177

August 22, 2024

How to get Backdoor Access for Memory?

UVM

RAL

0

159

August 8, 2024

Proper reg_map has not picked up

UVM

RAL

5

166

July 4, 2024

UVM register model

UVM

RAL , uvm-ral

0

148

July 1, 2024

RAL Register access

UVM

RAL

3

379

May 16, 2024

Skipping a register field from comparison with RAL

UVM

RAL , uvm_ral , RAL-UVM

10

744

May 15, 2024

Macro to read register fields using RAL

Coverage

UVM , Coverage , assertion , RAL , System-Verilog

1

325

March 26, 2024

How to use get_full_hdl_path for the register

UVM

RAL

0

473

March 15, 2024

RAL Backdoor access, set hdl paths

UVM

UVM , RAL

1

323

February 29, 2024

Question related to RAL methods

SystemVerilog

UVM , RAL , uvm_ral , RAL-UVM

0

308

February 26, 2024

How to access UVM_MEM using the .write method

UVM

UVM , RAL , uvm_mem

2

491

February 25, 2024

UVM RAL Memory - Sampling after read/write operation

UVM

SystemVerilog , Coverage , RAL , uvm_mem , Sampling

0

536

February 3, 2024

My question is how to verify “R0” (Read only) registers through backdoor or front door mechanism ? In frontdoor usually we do masking of RO registers to not to write .If RO register is designed with bug with RW type how to verify this issue without write

UVM

RAL

1

374

January 23, 2024

In UVM RAL, I have 2 active agentS,only one adaptor. how to work 2 transaction in one adaptor?

UVM

UVM , RAL , RAL-register-UVM , uvm-ral , UVM-RAL-systemverilog-ralmodelling , RAL-UVM

0

314

December 29, 2023

Access (to W/R) 2 Specific fields in a 32-bit register

UVM

RAL , uvm-ral , Systemverilog-UVM-RAL

1

330

December 27, 2023

RAL Integration

UVM

UVM , RAL , APB , vip-intergrate , register_model

0

408

December 11, 2023

I had an issue regarding RAL, i am unable to create a map which should contains maps of different invidual registers

UVM

UVM , RAL , RAL-UVM

0

321

December 6, 2023

Predicting Read Only Register in RAL

UVM

UVM , RAL , prediction-monitor-scoreboard , predictors

1

840

November 30, 2023

How to do Scoreboarding or checking the WR_data and read data matching in RAL

UVM

UVM , RAL

1

428

November 29, 2023

How to set a register to a value thru a hierarchy receiving as string?

UVM

UVM , RAL , accessing-the-associative-array-elements , systemverilog-Arrays

3

686

October 4, 2023

Environment and DUT random configuration

UVM

UVM , RAL , configuration , randomization , UVM-Environment

7

661

September 25, 2023

IN UVM RAL Adapter class, why do we use const ref for uvm_bus_reg_op in reg2bus and only ref for uvm_bus_reg_op in bus2reg?

UVM

UVM , RAL , adapter

1

330

August 25, 2023

Info regarding built in sequences for memory

UVM

UVM , RAL

6

706

May 23, 2023

What is the purpose of bus_req.end_event.wait_on(); in uvm_reg_map::do_bus_write

UVM

UVM , RAL

1

538

March 21, 2023

RAL: set_check_on_read(1) does not work with frontdoor access and passive prediction?

UVM

UVM , RAL , auto-prediction , set_check_on_read

0

704

March 9, 2023

DUPIDN compilation error for reg models

UVM

UVM , RAL , RAL-IPXACT , UVM-UVMRAL

0

357

February 27, 2023

UVM RAL sequences with priority

UVM

UVM , RAL , sequence-arbitration , sequencer-arbitration , UVM-RAL-SEQUENCE

4

935

February 15, 2023

Invalid Register access

UVM

UVM , RAL , uvm-register-model , -UVM-warnings-disable

4

905

February 6, 2023