Verification Academy

Topic	Replies	Views	Activity
Fatal error in NamedBeginStat chip_sim_pkg/pause_checker UVM UVM , systemverilog-uvm	2	634	February 1, 2022
SystemVerilog Timescale SystemVerilog SystemVerilog , Verilog-timescale-timeunit	1	1564	January 31, 2022
For the virtual interface handle to become valid, it must be assigned to a concrete static interface instance in the testbench module part of the testbench. Is it not the other way around? UVM UVM	1	524	January 31, 2022
Confusion regarding Failure of Assertion via "within" operator SystemVerilog SystemVerilog , Confusion-regarding-Failure-of-Assertion-via	3	770	January 30, 2022
Assertion to check stability of a signal for 'n' clocks SystemVerilog SystemVerilog , stability-of-a-signal	15	27130	January 29, 2022
Address calculation SystemVerilog SystemVerilog , constraint-randomization	1	898	January 29, 2022
Constraint for repeating numbers in an array in a unique pattern SystemVerilog SystemVerilog , constraint-randomization , systemverilog-Arrays	6	2218	January 28, 2022
Xyz.\signal_a[0][0] in the netlist cannot be accessed from testbench due to \ SystemVerilog SystemVerilog	7	1044	January 28, 2022
How to track a changes in a sequence in a UVM testbench? UVM UVM , driver , uvm-sequence-item , UVM-Sequence-Tracking	1	994	January 28, 2022
Detect randomization failure while using `uvm_do_with macro UVM SystemVerilog , UVM , uvm_do_with	1	613	January 27, 2022
OR Construct basics in Concurrent Assertions SystemVerilog SystemVerilog , OR-Construct-basics-in-Concurrent-Assertions	6	890	January 27, 2022
Get_response() in sequence, Giving error below: Any suggestions? I am trying to learn UVM features with very small & simple example UVM UVM , get_response , uvm--sequence	7	1391	January 27, 2022
Compare fields from two associative arrays SystemVerilog SystemVerilog , Compare-fields-from-two-Associative-Array	3	975	January 26, 2022
Property VS Sequence via Implicit first_match SystemVerilog SystemVerilog , Property-VS-Sequence	2	725	January 26, 2022
Difference uVC, IVC, VIP in design verification UVM UVM , test-uvm-coverage-	1	1426	January 26, 2022
Merging of Two interface UVM UVM , uvm-interface	4	895	January 26, 2022
What is the meaning of next code? SystemVerilog SystemVerilog	1	563	January 25, 2022
Uvm scoreboard, uvm_monitor and uvm_subscriber SystemVerilog SystemVerilog , UVM-scoreboard , uvm_monitor-and-uvm_subscriber	0	643	January 25, 2022
How to call one customized sequence from another customized seq? UVM UVM , uvm--sequence	1	1083	January 24, 2022
Packet generating UVM UVM , uvm-driver-valid-loop	3	883	January 24, 2022
Using the set_max_quit_count() method UVM UVM , Cookbook-MessagingUsingMessaging	1	1099	January 24, 2022
Constraint problem SystemVerilog SystemVerilog	9	2761	January 23, 2022
Error-[NOA] Null object access alu_env.sv, 44 The object at dereference depth 2 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it UVM UVM , Cookbook-Sequences	1	1130	January 23, 2022
Virtual testbench SystemVerilog SystemVerilog , VCD , Virtual-Testbench , Scan-test	1	509	January 23, 2022
EEnet type pins in Mixed Signal Chip SystemVerilog SystemVerilog , EEnet , Mixed-Signal-Design , Analog-Chip	1	728	January 23, 2022
Hypothetical question : what if there are major updates in my interface, creating new interface with different name but don't want to touch Driver & Monitor code UVM SystemVerilog , UVM , systemverilog-interface	2	807	January 22, 2022
Representing an Imaginary Number in SystemVerilog SystemVerilog SystemVerilog , mathematics , complex	3	1812	January 22, 2022
Passing queue through sequence_item UVM UVM , sequencer , sequence , driver , Queues , sequence-item	2	1373	January 22, 2022
Request - Acknowledge related Assertion SystemVerilog SystemVerilog , Request-Acknowledge-related-Assertion	7	1566	January 21, 2022
Cant we use Constraints in Post_randomize method? UVM UVM , uvm_object_utils , pre_randomize-amp-post_randomize-function	1	954	January 21, 2022