SystemVerilog Timescale

SystemVerilog
,
1

In my testbench, I am generating two clocks - clk_50M and clk_161_132812 - as shown in the code below. When I simulate (with QuestaSim 2021.3), I see clk_50M generated with 20ns period as expected. However, clk_161_132812 get generated with 6206.06 nanosecond period instead of 6.20606ns. But if remove ‘fs’ timeunit (i.e. use #3103030.303 instead of #3103030.303fs), the clock is generated with the correct period. What’s going on?

`timescale 1fs/1fs
module tb;
   
   bit clk_50M;
   bit clk_161_132812M;

   always #10000.000ps clk_50M = ~clk_50M;
   always #3103030.303fs clk_161_132812M = ~clk_161_132812M;
   
endmodule
2

In reply to Earthling:

Note that it’s not possible to represent factional femtoseconds in SystemVerilog as 1 femtosecond is the smallest possible integral value for a time value.

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