Property VS Sequence via Implicit first_match

SystemVerilog
,
1

I was referring to SNUG09 paper " If Chained Implications in Properties Weren’t So Hard, They’d be Easy " by Don Mills

It has following line ::


One difference between a property and a sequence is that property expressions contain an
implicit first-match whereas a sequence does not. This means that if a sequence has multiple
pass conditions, then each will occur. However, when that same sequence is placed in a property
expression, only the first pass condition of the sequence will be observed by the property, ending
that thread.

Need help trying to understand the above line .

I tried following Code :: EDA_LINK

However I don’t observe any difference in O/P with OR without +define+PROP .

2

In reply to hisingh:

I think what the author meant by “implicit first-match” is if a multi-thread sequence is at the consequent part, it is implicit first match.

3

In reply to Jeff_Li_90:
I downloaded Don’s paper from https://lcdm-eng.com/papers/mentor09_U2U%202009%20presentation_v02.pdf
I did not see that quote. It’s a good paper.
Adding a comment to Jeff’s reply, in a consequent you are looking for a pass.


 a |-> ##[1:3] b; // equivalent to a |-> ##1 b or ##2 b or ##3 b; 
// If "b: is true one cycle after "a", there is no need to test for the ##2 b or the ##3 b 
//  because if those pass or fail, it does not matter. True or False == TRUE
//                                                     True or true  == true

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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