I was trying a code via “within” operator :: EDA_LINK
In both cases +define+M1 OR +define+M2 , there is a violation of the LHS of the “within” operator
However the Failure is reported at different TIME across different simulators .
What does the LRM say when should the Failure be reported ?? As in at what exact time ?
Should it wait for the RHS ( i.e the longer sequence ) to end to report the failure ??
In reply to hisingh:
(seq1 within seq2) is equivalent to:
((1[*0:$] ##1 seq1 ##1 1[*0:$]) intersect seq2 )
What does the LRM say when should the Failure be reported ?
It does not say when, it is up to the tool.
In reply to ben@SystemVerilog.us:
I disagree. The action block of an assertion gets executed in the re-active region after the observed region where the assertion evaluates and fails.
In reply to dave_59:
I believe the author was asking at which cycle the failure is displayed.
His assertion looked like:
@ (posedge clk) $fell(bMode) |=> // stack within smtrx ;
($fell(tack) ##0 !tack[*7]) within ($fell(mtrx) ##0 !mtrx[*9]);
If the waveform was something like ($fell(tack) ##0 !tack[*6] ##1 tack)
The failure would occur at the endpoint of ($fell(mtrx) ##0 !mtrx[*9]).
But I believe the failure can be shown at the endpoint of
($fell(tack) ##0 !tack[*6] ##1 tack)
1800 does not specify at which cycle the failure needs to be declared. Isn’t that a tool thing?
Ben