Hi…can anyone tell me what is a Virtual Testbench & How it is used with vcd file to test chip before tapeout? And also i want to understand the meaning of performing scan test before tapeout ?
In reply to shekher201778:
You will have to ask the source from where you saw this term. For people used to testing FPGAs in a lab with probes, a virtual testbench is just what you use for simulation. But there could be other meanings.