Verification Academy

Topic	Replies	Views	Activity
How to reuse the agent , if multiple channels , let say 3 channels are present at phy layer? UVM UVM , mutilple-agent-for-the-same-bus-protcol	3	387	October 29, 2022
Write an assertion where in if a signal A goes high in one cycle, signals B and C should go low in the same cycle SystemVerilog SystemVerilog	2	1459	October 28, 2022
Why error when using process::self() in static task SystemVerilog SystemVerilog , Systemverilog-process	1	734	October 28, 2022
Constraint solver error SystemVerilog SystemVerilog	1	343	October 28, 2022
How do I get all transferred data by uvm_analysis_port? UVM UVM , uvm_tlm_analysis_fifo	3	614	October 27, 2022
If error comes then test will displayed as pass UVM UVM , SV , APB , ERROR_PASS	4	901	October 27, 2022
Unable to set/get an interface which has a struct as a parameter UVM UVM , uvm_config_db-interfaces	2	430	October 27, 2022
Disabling phases for child components UVM UVM	3	554	October 27, 2022
Ignore bins - Cross coverage SystemVerilog SystemVerilog	1	388	October 27, 2022
Assertion to check Synchronous de-assertion SystemVerilog SystemVerilog , Assertion-to-check-Synchronous-de-assertion	3	1186	October 26, 2022
Fail problem SystemVerilog SystemVerilog	7	806	October 25, 2022
Constraint solver issue while dealing with dynamic array size randomization UVM UVM , systemverilog-constraint , uvm-dynamicarray	2	642	October 25, 2022
Unable to find the specification for the DUTs considered in the UVMF examples Downloads Downloads , UVMF-20221 , UVMF_36G-ahb2wb-example	2	647	October 25, 2022
Distribution constraint: Value is not getting distributed as per the weight SystemVerilog SystemVerilog , systemverilog-distribution-constraints	1	450	October 25, 2022
Race condition between get_next_item and @clk UVM UVM , get_next_item , uvm-uvm_driver- , clocking-blocks-skews-event-regions	2	556	October 25, 2022
Questions about disabling random variables with rand_mode() SystemVerilog SystemVerilog , rand_mode	1	844	October 24, 2022
How to get multiple uvm_analysis_port with uvm_analysis_imp_decl? UVM UVM	3	676	October 24, 2022
The best way of using struct, class, and array SystemVerilog SystemVerilog , class , performance , simulation-performance	4	1195	October 24, 2022
Calling predict() for registers UVM UVM , Calling-predict-for-registers	0	442	October 23, 2022
Large Simulation Time Coverage Coverage , simulation-time	1	465	October 23, 2022
Do uvm_hdl_deposit works on net data types? UVM UVM	1	341	October 23, 2022
UVM built in register sequenes on a null sequencer? UVM UVM	3	623	October 21, 2022
Upcasting application! UVM UVM , upcasting	0	325	October 21, 2022
How to update the register model in uvm, when registers gets updated by the design internally and not through a bus access UVM UVM , assertion , RAL-UVM-PREDICTOR	2	449	October 21, 2022
Can we pass signal reference through config_db? UVM UVM , uvm_object-and-config-db-get	1	334	October 21, 2022
Dynamic assignment of a byte value in a vector in a simulation SystemVerilog SystemVerilog , signal_force , range-must-be-bounded	1	518	October 20, 2022
Write constraints for AHB HSize with 10 times inc4, then 20 times inc16 and then 40 times wrap? UVM UVM , System-Verilog , AHB , uvm-sv-constraints	0	474	October 20, 2022
Run a task but suppress all the $display statements? SystemVerilog SystemVerilog	1	391	October 20, 2022
Adding functionality inside write method of UVM analysis port UVM UVM , System-Verilog , UVM-ports , uvm-analysis-implementation , base_test-uvm_tlm_fifo	1	633	October 19, 2022
How to check if different signals are asserted in order? SystemVerilog SystemVerilog , UVM , assertion , System-Verilog , SVA , property	1	610	October 19, 2022