Constraint solver error

SystemVerilog
1

I have array of uvm_object say a[4]

class a;
  rand int mod_size[];
  rand int trans_cnt;

  constraint mod_size_constr{
    mod_size.size == trans_cnt;
  }

  constraint trans_cnt_constr{
     trans_cnt == 10; by default it is 0 in main class. in test case i have it constrianted to 10 here.
  }

endclass

I get solver error for array size for mod_size really big even though I have constraint to have it equal to the trans_cnt

Can you help to understand why I get the solver error.

I modified my solver error message to keep confidentiality of my structure… Hope you can still understand what the error is.
Solver failed when solving following set of constraints

rand integer a[4].progressive_mode = 1; // rand_mode = OFF 
rand integer a[4].trans_cnt; // rand_mode = ON 
rand bit[30:0] a[4].vfp_mod.size() = 31'h15958e2; // rand_mode = OFF 

constraint dyn_rr_base_constr    // (from a[4]) (constraint_mode = ON) 
{
   (a[4].vfp_mod.size() == a[4].trans_cnt;
}
constraint trans_cnt_constr    

{
   a[4].trans_cnt == 20;
}

Thanks
Kanmani S

2

In reply to Ksubramanian:

You are not showing enough code for us to help you. Show us the top level class that has instantiates a[4] and puts constraints on the size of the array.