How to get multiple uvm_analysis_port with uvm_analysis_imp_decl?

UVM
1

Hi.

As I understand about uvm_analysis_imp_decl, it used for multiple analysis_imp.
https://verificationacademy.com/forums/uvm/uvmanalysisimpdecl

Trying to understand uvm_analysis_imp_decl I made a simple example.



`uvm_analysis_imp_decl(_port_a)
`uvm_analysis_imp_decl(_port_b)
`uvm_analysis_imp_decl(_port_c)

class component_b extends uvm_component;
  
  transaction trans;
  uvm_analysis_imp_port_a #(transaction,component_b) analysis_imp_a;  
  uvm_analysis_imp_port_b #(transaction,component_b) analysis_imp_b;
  uvm_analysis_imp_port_c #(transaction,component_b) analysis_imp_c;
  
  `uvm_component_utils(component_b)
  
  //--------------------------------------- 
  // Constructor
  //---------------------------------------
  function new(string name, uvm_component parent);
    super.new(name, parent);
    analysis_imp_a = new("analysis_imp_a", this);
    analysis_imp_b = new("analysis_imp_b", this);
    analysis_imp_c = new("analysis_imp_c", this);

  endfunction : new
  
  //---------------------------------------
  // Analysis port write method
  //---------------------------------------
  virtual function void write_port_a(transaction trans);
    `uvm_info(get_type_name(),$sformatf(" Inside write_port_a method. Recived trans On Analysis Imp Port"),UVM_LOW)
    `uvm_info(get_type_name(),$sformatf(" Printing trans, \n %s",trans.sprint()),UVM_LOW)
  endfunction 
  
  //---------------------------------------
  // Analysis port write method
  //---------------------------------------
  virtual function void write_port_b(transaction trans);
    `uvm_info(get_type_name(),$sformatf(" Inside write_port_b method. Recived trans On Analysis Imp Port"),UVM_LOW)
    `uvm_info(get_type_name(),$sformatf(" Printing trans, \n %s",trans.sprint()),UVM_LOW)
  endfunction
  //---------------------------------------
  // Analysis port write method
  //---------------------------------------
  virtual function void write_port_c(transaction_c trans_c);
    `uvm_info(get_type_name(),$sformatf(" Inside write_port_c method. Recived trans On Analysis Imp Port"),UVM_LOW)
    `uvm_info(get_type_name(),$sformatf(" Printing trans_c, \n %s",trans_c.sprint()),UVM_LOW)
  endfunction
  
endclass : component_b





`include "transaction.sv"
`include "transaction_c.sv"
`include "component_a.sv"
`include "component_b.sv"
`include "component_c.sv"

class environment extends uvm_env;
  
  //---------------------------------------
  // Components Instantiation
  //---------------------------------------
  component_a comp_a;
  component_b comp_b;
  component_c comp_c;
  `uvm_component_utils(environment)
  
  //--------------------------------------- 
  // Constructor
  //---------------------------------------
  function new(string name, uvm_component parent);
    super.new(name, parent);
  endfunction : new

  //---------------------------------------
  // build_phase - Create the components
  //---------------------------------------
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);

    comp_a = component_a::type_id::create("comp_a", this);
    comp_b = component_b::type_id::create("comp_b", this);
    comp_c = component_c::type_id::create("comp_c", this);
  endfunction : build_phase
  
  //---------------------------------------
  // Connect_phase 
  //---------------------------------------
  function void connect_phase(uvm_phase phase);
    comp_a.analysis_port.connect(comp_b.analysis_imp_a);
    comp_a.analysis_port.connect(comp_b.analysis_imp_b);
    comp_c.analysis_port.connect(comp_b.analysis_imp_c);
  endfunction : connect_phase
endclass : environment

But I got the error.

# ** Error: (vsim-7065) Illegal assignment to class /usr/share/questa/questasim//uvm-1.2.uvm_pkg::uvm_port_base #(class /usr/share/questa/questasim//uvm-1.2.uvm_pkg::uvm_tlm_if_base #(class work.testbench_sv_unit::transaction_c, class work.testbench_sv_unit::transaction_c)) from class work.testbench_sv_unit::uvm_analysis_imp_port_c #(class work.testbench_sv_unit::transaction, class work.testbench_sv_unit::component_b)
#    Time: 0 ns  Iteration: 0  Region: /testbench_sv_unit File: environment.sv Line: 44
# ** Error: (vsim-8754) Actual input arg. of type 'class work.testbench_sv_unit::uvm_analysis_imp_port_c #(class work.testbench_sv_unit::transaction, class work.testbench_sv_unit::component_b)' for formal 'provider' of 'connect' is not compatible with the formal's type 'class /usr/share/questa/questasim//uvm-1.2.uvm_pkg::uvm_port_base #(class /usr/share/questa/questasim//uvm-1.2.uvm_pkg::uvm_tlm_if_base #(class work.testbench_sv_unit::transaction_c, class work.testbench_sv_unit::transaction_c))'.
#    Time: 0 ns  Iteration: 0  Region: /testbench_sv_unit File: environment.sv Line: 44
# Error loading design

I can’t understand “comp_c.analysis_port.connect(comp_b.analysis_imp_c);” why does it make error?

2

In reply to UVM_LOVE:

The error message tells me the parameterization doesn’t match between the port and implementation

How have you declared analysis_port within component_a , component_b and component_c ?

3

In reply to ABD_91:

In reply to UVM_LOVE:
The error message tells me the parameterization doesn’t match between the port and implementation
How have you declared analysis_port within component_a , component_b and component_c ?

I made a link for understand my problem.

4

In reply to UVM_LOVE:

The analysis_port in component_c is parameterized with ‘transaction_c’. The analysis_imp_port is parameterized with ‘transaction’. Since the transactions aren’t type-compatible, you can’t connect them.

You need to fix the analysis_imp_port in component_b to use the correct ‘transaction_c’.