I pass a parameter from above about which byte from the vector to perform a certain operation on
How can I put a mask on it normally in the Verilog ?
I have it done this way now, but he swears, like it’s done dynamically, but he can’t do it like that
task force_release(input int num_of_byte);
begin
$display("DATA BEFORE = %0h", dut.dut.link_layer.stream_to_header_analyzer.data[0]);
if(dut.dut.link_layer.stream_to_header_analyzer.data[0][3+8*(num_of_byte-1):10+8*(num_of_byte-1)] != 0)
begin
force dut.dut.link_layer.stream_to_header_analyzer.data[0][3+8*(num_of_byte-1):10+8*(num_of_byte-1)]='h0;
end
else
begin
force dut.dut.link_layer.stream_to_header_analyzer.data[0][3+8*(num_of_byte-1):10+8*(num_of_byte-1)]='hFF;
end
wait(dut.dut.link_layer.stream_to_header_analyzer.valid == 1); @(posedge rx_clk_w); #0.1ns;
$display("DATA AFTER = %0h", dut.dut.link_layer.stream_to_header_analyzer.data[0]);
release dut.dut.link_layer.stream_to_header_analyzer.data[0];
end
endtask
The vector is 67 - bit
The first 3 bits are control bits, that is, starting from the 4th bit in the vector
Now I have this error:
Range must be bounded by constant expressions.