How to update the register model in uvm, when registers gets updated by the design internally and not through a bus access

if registers are internally updated by the CPU, and we want to monitor that cpu write activity and update the register model in parallel, How do we do it?

In reply to sumanth291092:

A register that is modified internally by the design is normally considered a read-only (RO) register. The register model will be updated when you read the register.

Using the task mirror