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October 2013

Interrupts_prioritised.tgz
Standards Oct 07, 2013 tar
Interrupts_simple.tgz
Standards Oct 07, 2013 tar
Overriding.tgz
Standards Oct 07, 2013 tar
Priority_arbitration.tgz
Standards Oct 07, 2013 tar
Priority_grab_lock.tgz
Standards Oct 07, 2013 tar
QVIP Express (.tgz)
UVM - Universal Verification Methodology Oct 07, 2013 tar
Tb_build_ss_tb.tgz
Standards Oct 07, 2013 tar
Use_models_bidir_get_put_uvm.tgz
Standards Oct 07, 2013 tar
Use_models_bidir_item_done_uvm.tgz
Standards Oct 07, 2013 tar
Bidirectional Sequence Driver Use Model (.tgz)
UVM - Universal Verification Methodology Oct 07, 2013 Verification Methodology Team tar
Use_models_pipelined_get_put.tgz
Standards Oct 07, 2013 tar
Use_models_pipelined_item_done.tgz
Standards Oct 07, 2013 tar
Use_models_tb_build_tbx_uvm.tgz
Standards Oct 07, 2013 tar
Use_models_unidirectional.tgz
Standards Oct 07, 2013 tar
Uvm_Abstract-concrete.tgz
Standards Oct 07, 2013 tar
Uvm_generation_seq_persistence.tgz
Standards Oct 07, 2013 tar
Uvm_generation_seq_poly.tgz
Standards Oct 07, 2013 tar
Uvm_generation_seq_rand.tgz
Standards Oct 07, 2013 tar
Uvm_interrupts_prioritised.tgz
Standards Oct 07, 2013 tar
Uvm_mem_example.tgz
Standards Oct 07, 2013 tar
Verification Horizons - Volume 9, Issue 3
Standards Oct 01, 2013 Tom Fitzpatrick pdf
Basic UVM Code Examples
UVM - Universal Verification Methodology Oct 01, 2013 Verification Methodology Team tar

September 2013

The Need for Speed: Understanding Design Factors that Make Multi-core Parallel Simulations Efficient
Simulation Sep 19, 2013 Shobana Sudhakar Article
UVM Connect Guide
UVMC Sep 08, 2013 Adam Erickson pdf

August 2013

UVM Register Model CSV Example
UVM - Universal Verification Methodology Aug 15, 2013 Tom Fitzpatrick tar

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Regression Webinar

Wednesday, Feb 12th-8:00 AM PST

Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Simulation Webinar

Unlocking the Power of QuestaSim and Visualizer Integration

VA Live: El Segundo

Thursday, Feb 06th-9:30 AM PST

Formal Security Verification, AI/ML, RTL Simulation, and more

Safety & Security Webinar

Wednesday, Feb 19th-8:00 AM PST

FPGA Equivalence Checking from RTL to the Bitstream

Formal Security Webinar

Explore How to Protect Against Data Corruption with Formal Security Verification

Functional Safety Webinar

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

Debug Webinar

Wednesday, Mar 05th-8:00 AM PST

Faster Debug of Complex Testbenches Using Visualizer

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