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June 2014

Use of Iterative Weight-Age Constraint to Implement Dynamic Verification Components
Simulation Jun 18, 2014 Verification Horizons Article
UVM Testbench Structure and Coverage Improvement in a Mixed Signal Verification Environment
Standards Jun 18, 2014 Verification Horizons Article
Making it Easy to Deploy the UVM
Standards Jun 17, 2014 Verification Horizons Article
Verifying High Speed Peripheral IPs
Simulation Jun 17, 2014 Verification Horizons Article
Non-invasive Software Verification Using Vista Virtual Platforms
Functional Safety Jun 17, 2014 Verification Horizons Article
Optimizing Emulator Utilization
Acceleration Jun 16, 2014 Russell Klein Article
UVM 1.2 Class Reference
UVM - Universal Verification Methodology Jun 13, 2014 html
Stories of an AMS Verification Dude: Putting Stuff Together
Analog Mixed-Signal Jun 12, 2014 Verification Horizons Article
Taming Power Aware Bugs with Questa®
Standards Jun 12, 2014 Verification Horizons Article
Assertions Instead of FSMs/logic for Scoreboarding and Verification
SystemVerilog Jun 12, 2014 Ben Cohen Article
DDR SDRAM Bus Monitoring using Mentor Verification IP
Simulation Jun 12, 2014 Verification Horizons Article
Simulation + Emulation = Verification Success
Simulation Jun 12, 2014 Verification Horizons Article

May 2014

UVM 1.2 is Coming, so be Prepared
UVM - Universal Verification Methodology May 15, 2014 Tom Fitzpatrick Webinar

March 2014

Verification Cookbook Glossary
UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter
Sequence Library
UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter
Convert Phase Methods
UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter
Migrating from OVM to UVM
UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter
Questa Compiling UVM
UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter
Deprecated Code
UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter
Phase Aware
UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter
Arbitrating Between Sequences
UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter
UVM Configuration Database
UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter
Sequence API
UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter
Reporting Verbosity
UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter
Built in Debug
UVM - Universal Verification Methodology Mar 31, 2014 Verification Methodology Team Chapter

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Regression Webinar

Wednesday, Feb 12th-8:00 AM PST

Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Simulation Webinar

Unlocking the Power of QuestaSim and Visualizer Integration

VA Live: El Segundo

Thursday, Feb 06th-9:30 AM PST

Formal Security Verification, AI/ML, RTL Simulation, and more

Safety & Security Webinar

Wednesday, Feb 19th-8:00 AM PST

FPGA Equivalence Checking from RTL to the Bitstream

Formal Security Webinar

Explore How to Protect Against Data Corruption with Formal Security Verification

Functional Safety Webinar

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

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