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August 2014

Object Oriented Programming
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi Session
SystemVerilog Interfaces
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi pdf
SystemVerilog Interfaces
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi Session
Packages, Includes and Macros
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi pdf
Packages, Includes and Macros
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi Session
UVM Components and Tests
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi pdf
UVM Components and Tests
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi Session
UVM Environments
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi pdf
UVM Environments
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi Session
Connecting Objects
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi Session
Connecting Objects
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi pdf
Transaction Level Testing
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi Session
Transaction Level Testing
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi pdf
The Analysis Layer
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi pdf
The Analysis Layer
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi Session
UVM Reporting
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi Session
UVM Reporting
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi pdf
Functional Coverage with Covergroups
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi Session
Functional Coverage with Covergroups
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi pdf
Introduction to Sequences
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi Session
Introduction to Sequences
UVM - Universal Verification Methodology Aug 06, 2014 Ray Salemi pdf
Introduction to the UVM
UVM - Universal Verification Methodology Aug 04, 2014 Ray Salemi Track

July 2014

ST-Ericsson Speeds Time to Functional Verification Closure with Questa Verification Platform
Simulation Jul 10, 2014 Verification Horizons Article
There's Productivity. And Then There's Productivity
Simulation Jul 10, 2014 Verification Horizons Article

June 2014

UVM: What's New, What's Next and Why You Care
UVM - Universal Verification Methodology Jun 25, 2014 Tom Fitzpatrick Webinar

FPU Webinar

Wednesday, Feb 05th-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Regression Webinar

Wednesday, Feb 12th-8:00 AM PST

Smart Regression: Optimize Regression Efficiency Using Questa Verification IQ Regression Navigator

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Simulation Webinar

Unlocking the Power of QuestaSim and Visualizer Integration

VA Live: El Segundo

Thursday, Feb 06th-9:30 AM PST

Formal Security Verification, AI/ML, RTL Simulation, and more

Safety & Security Webinar

Wednesday, Feb 19th-8:00 AM PST

FPGA Equivalence Checking from RTL to the Bitstream

Formal Security Webinar

Explore How to Protect Against Data Corruption with Formal Security Verification

Functional Safety Webinar

An End-to-End Functional Safety Solution for Automotive ICs Based on ISO 26262

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

Debug Webinar

Wednesday, Mar 05th-8:00 AM PST

Faster Debug of Complex Testbenches Using Visualizer

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