Topics tagged ral

Topic	Replies	Views	Activity
RAL read and auto_predict UVM UVM , RAL	0	506	May 4, 2022
Hanging register write UVM UVM , RAL , Write , hang , UVM_IS_OK	1	475	April 16, 2022
Combining all reg_models into one UVM UVM , RAL , systemverilog-uvm , UVM-RAL-UVM	3	863	March 7, 2022
RAL read and write issues to Design UVM UVM , RAL , RAL-UVM	9	1220	March 7, 2022
Functions inside apb adapter are not being called from the test sequence UVM UVM , RAL , RAL-UVM , uvmral	2	653	February 23, 2022
What is difference between set_cfg and configure method in ral? OVM OVM , RAL	1	661	February 3, 2022
RAL mirror() method with UVM_CHECK not printing error messages UVM UVM , RAL , mirror , UVM_CHECK	0	680	October 26, 2021
$cast failed using parameterised uvm_sequence_item class UVM SystemVerilog , UVM , RAL , OOP	8	1562	October 14, 2021
How do you assign different sequencers to different reg_map? UVM UVM , RAL , uvm_reg_map	0	621	September 23, 2021
How do I get multiple transactions if register width is wider or narrower than bus width? UVM SystemVerilog , UVM , RAL	0	633	June 5, 2021
UVM_RAL: Why Predictor calling bus2reg function(Adapter) 2 times automatically? UVM UVM , RAL , Mirrored-values-and-desired-values-in-UVM-RAL	10	4351	February 19, 2020
Setting endianness for every uvm_reg UVM UVM , RAL	2	1359	April 9, 2019
RAL :: get_reg_by_offset() method UVM UVM , RAL , uvm-ral	4	5653	November 14, 2018
[RAL] Problems with Memory Frontdoor Write UVM UVM , RAL , frontdoor , memory	0	1987	September 11, 2018
Uvm_mem access UVM UVM , RAL , mem	5	1864	August 27, 2018
One register map for multiple agents? UVM UVM , RAL , uvm_reg_map , register-adapter	4	3027	June 29, 2018
UVM Register layer writing/reading X values UVM UVM , RAL , register-layer , x-value	5	2146	June 19, 2018
UVM_REG_BLOCK from UVM_REG UVM UVM , RAL , uvm_reg	1	2766	May 22, 2018
UVM_RAL Frontdoor methods UVM UVM , RAL , backdoor , uvm_reg_sequence , frontdoor	1	1975	April 24, 2018
RAL - clear on read registers UVM UVM , RAL	7	2945	April 18, 2018
RAL: uvm_reg_map base address does not work UVM UVM , RAL , uvm_reg_block , uvm_reg_map , m_base_addr	3	2389	March 5, 2018
UVM RAL LIBRARY BUG OR UVM UVM , RAL , CHECK_ON_READ , DO_CHECK	4	1623	March 1, 2018
How to set_compare(UVM_NO_CHECK) to individual bits of register fields? UVM UVM , RAL , UVM_NO_CHECK , set_compare , bit_access , backdoor_check	2	4714	February 27, 2018
UVM RAL, PIPELINE, BACK TO BACK UVM UVM , RAL , Pipelined , AHB , back2back	2	1621	February 12, 2018
How to update the mirror value of register UVM UVM , RAL , Mirrored-values-and-desired-values-in-UVM-RAL , mirrored-value , register-read-mirror-set_check_on_read	13	14090	February 9, 2018
Register Addressing RAL UVM UVM , RAL , Advanced-UVM-Register	0	1227	September 8, 2017
Broadcast register read/write with RAL UVM UVM , RAL , UVM-callback , Advanced-UVM-Register	1	1882	September 7, 2017
Changing sequemcer handle in reg_seqs still triggers register writes UVM UVM , RAL	10	1628	May 15, 2017
UVM_RAL::Linking Mirror models for a register accessible through two addresses on the same physical interface UVM UVM , RAL , uvm-register-w1c , Mirror-Model , uvm-register-w1s	0	1015	April 20, 2017
How to make some registers of DUT as not Accessible to the customer UVM UVM , RAL , RTL , Cookbook-RegistersRegisterModelOverview , Advanced-UVM-Register	3	1697	November 14, 2016