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System verilog assertion to check that signal 'a' takes a value only when it has taken some other particular value before
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11
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12149
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May 24, 2021
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Error regarding factory.print()
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12
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6519
|
September 15, 2016
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How to use a "soft constraint" in OVM in sequence libary?
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17
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9744
|
November 29, 2013
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Report phase
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12
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11464
|
November 5, 2019
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Factory Instance Override problem
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15
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10193
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May 21, 2008
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Connect a sequence to a sequencer
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10
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12257
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May 25, 2011
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Use the output of a module inside a class (including task (generator)
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50
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5684
|
May 20, 2016
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Uvm reg read from uvm-monitor
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30
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7284
|
June 3, 2021
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Virtual Interface Assign Question
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17
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9533
|
June 17, 2009
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Ovm Error Report Messages
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10
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12169
|
February 27, 2009
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Timing checks or assertion checks
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9
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12735
|
March 9, 2016
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Interface hookup with Hierarchy of Components
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20
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8774
|
November 20, 2009
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Forever loop break
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17
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9280
|
April 21, 2023
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Objection Mechanism and simulation timeout
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13
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10407
|
December 30, 2010
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Error messages - from assertions
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9
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12234
|
August 22, 2008
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Not be able to access type override object properties?
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12
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10684
|
January 3, 2025
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Doubt regarding Simvision:
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9
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12160
|
July 28, 2008
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Effect of clocking block on uvm driver/monitor
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19
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8542
|
May 19, 2021
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Connecting the agent and scoreboard
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14
|
9786
|
September 22, 2015
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How to set_sequencer & adapter for the default maps present in the sub-blocks, which is instanced inside top level register blocks?
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9
|
11945
|
February 16, 2019
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Multiple UVC's/agents
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11
|
10864
|
June 6, 2018
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How to bind an interface with system verilog module?
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9
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11689
|
September 15, 2016
|
|
Tutorial for Gate Level Simulation
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9
|
11629
|
August 17, 2019
|
|
Cross coverage of two covergroups
|
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9
|
11590
|
April 4, 2014
|
|
Having issues with wait statements
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9
|
11571
|
November 8, 2018
|
|
Runtime Fatal Error : p_sequencer can't be casting from a parameterized sequencer
|
|
9
|
11541
|
June 4, 2017
|
|
UVM wrapper for a VMM VIP
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|
10
|
10810
|
May 11, 2012
|
|
Dynamic Arrays with ovm_do_with & ovm_do_on_with
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9
|
11291
|
December 22, 2010
|
|
Why not use program block
|
|
9
|
11215
|
July 4, 2008
|
|
Register Classes for SystemVerilog OVM
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18
|
8134
|
February 11, 2011
|
|
Change mirror value of a register field before running uvm_reg_hw_reset_seq
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17
|
8302
|
October 16, 2017
|
|
Accessing base class function using derived class object/handle in systemverilog
|
|
10
|
10512
|
July 3, 2020
|
|
Assertion to check signal is toggling or not
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|
10
|
10456
|
August 30, 2024
|
|
When should be program block dynamic or static ? members of static program block , members of automatic program blocks?
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14
|
8936
|
July 8, 2020
|
|
Where to implement functional coverage
|
|
12
|
9580
|
July 15, 2020
|
|
Overriding with parameterized class
|
|
10
|
10404
|
October 8, 2009
|
|
How to give feedback to sequence
|
|
18
|
7707
|
April 7, 2010
|
|
Hierarchical reference not allowed from within a package
|
|
12
|
9296
|
June 24, 2008
|
|
UVM transaction recording in Questasim
|
|
10
|
10081
|
March 2, 2013
|
|
How does UVM Comparator works?
|
|
14
|
8476
|
October 7, 2017
|
|
OVM report messaging for assertions
|
|
17
|
7641
|
July 9, 2008
|
|
Round robin assertion
|
|
9
|
10233
|
March 26, 2024
|
|
Not able to Configure
|
|
11
|
9316
|
August 23, 2012
|
|
SV assertions for common design components with multiple instances
|
|
14
|
8283
|
August 16, 2017
|
|
Leaf level sequencer's stop_sequences() is terminating virtual sequence which is running on virtual sequencer
|
|
9
|
10119
|
December 5, 2017
|
|
UVM World site now open
|
|
9
|
10078
|
July 14, 2010
|
|
Cross coverage for transition bins, with each bin containing more than 1 value in it
|
|
9
|
10036
|
October 27, 2020
|
|
IUS version for OVM
|
|
11
|
8980
|
July 24, 2008
|
|
Physical interface inside a class
|
|
10
|
9291
|
November 16, 2017
|
|
OVM Cookbook?
|
|
21
|
6524
|
August 25, 2010
|