Not able to Configure

UVM
1

Hi Frds,

I did UVM verification environment of FIFO. But I got the fatal message “Not able to Configure” while running.

AGENT
*****
local wrapper wiff;
local virtual intf intf_01;
function void connect_phase(uvm_phase phase);
  super.connect_phase(phase);

   if(!get_config_object ("wiff",obj,0))
   begin
  `uvm_fatal(get_type_name(),"Not able to configure");
   end
   else begin
   if(!$cast(wiff , obj))
    begin
     `uvm_fatal(get_type_name(),"Object is not correct type");
    end
   else
    intf_01 = wiff.intf_01;
    end
    if(is_active == UVM_ACTIVE)
    begin
       driver.seq_item_port.connect(sequencer.seq_item_export);
    driver.intf_0 = wiff.intf_01;
    end
endfunction

TOP
*****
wrapper wif;

initial begin
  wif = new();
  wif.set_wrapper(intf_01);
  set_config_object("uvm_test_top.env.ag1", "wrapper", wif,0);
// uvm_config_db # (wrapper)::set(null,"uvm_test_top.env.ag1" , "wiff",wif) ;
 run_test("base_test");
 #200; $finish;
 // #2000 global_stop_request;
end

Please guide me to solve this issue.

Thanks & Regards,
P.Masilamani Raja

2

You are setting “wrapper” and getting “wiff”

Also look at the path reported by `uvm_fatal and make sure it matches that you used to set_config.

3

In reply to dave_59:

Hi

Thanks for your reply.

I have tried with “wiff” instead of wrapper, that time also got same error.

I got the error message in agent module. Agent code for your reference.

uvm_object obj;
local wrapper wiff;

 fifo_driver driver;
 fifo_sequencer sequencer;
local virtual intf intf_01;

protected uvm_active_passive_enum is_active ;

 function new (string name = "tc_fifo_agent", uvm_component parent = null);
  super.new(name , parent);
endfunction


function void build_phase(uvm_phase phase);
int is_active_val = 0;
  super.build_phase(phase);

if(!get_config_int ("is_active", is_active_val))
begin
  this.is_active = uvm_active_passive_enum'(is_active_val);
end
   if(is_active == UVM_ACTIVE)
    begin
     driver = fifo_driver::type_id::create("driver",this);
     sequencer = fifo_sequencer::type_id::create("sequencer",this);
    end
endfunction


function void connect_phase(uvm_phase phase);
  super.connect_phase(phase);

   if(!get_config_object ("wiff",obj,0))
   begin
  `uvm_fatal(get_type_name(),"Not able to configure");
   end
   else begin
   if(!$cast(wiff , obj))
    begin
     `uvm_fatal(get_type_name(),"Object is not correct type");
    end
   else
    intf_01 = wiff.intf_01;
    end
    if(is_active == UVM_ACTIVE)
    begin
       driver.seq_item_port.connect(sequencer.seq_item_export);
    driver.intf_0 = wiff.intf_01;
    end
endfunction

Please guide me.

4

In reply to MasilamaniRaja:

Can you show the complete error message?

5

In reply to dave_59:

Hi ,

UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(215) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2

UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(217) @ 0: reporter [Questa UVM] questa_uvm::init(+struct)

UVM_INFO @ 0: reporter [RNTST] Running test base_test…

********* Initialized values at Reset *********

UVM_INFO @ 0: uvm_test_top.env [uvm_test_top.env] Build

UVM_FATAL ../testbench/fifo_agent.sv(45) @ 0: tc_fifo_agent [uvm_agent] Not able to configure

— UVM Report Summary —

** Report counts by severity

UVM_INFO : 4

UVM_WARNING : 0

UVM_ERROR : 0

UVM_FATAL : 1

** Report counts by id

[Questa UVM] 2

[RNTST] 1

[uvm_agent] 1

[uvm_test_top.env] 1

** Note: $finish : /tools/questa10.1a/questa_sim/linux/../verilog_src/uvm-1.1a/src/base/uvm_report_object.svh(277)

Time: 0 ns Iteration: 16 Region: /uvm_pkg::uvm_phase::m_run_phases

1

Break in Function uvm_pkg/uvm_report_object::die at /tools/questa10.1a/questa_sim/linux/../verilog_src/uvm-1.1a/src/base/uvm_report_object.svh line 277

6

In reply to MasilamaniRaja:

The error message shows that it is generated from path “tc_fifo_agent”, yet you are setting the path "“uvm_test_top.env.ag1”.

Can you explain why the agent is not part of any hierarchy? Maybe you need to show the code that creates the hierarchy.

7

In reply to dave_59:

Hi

I have set the path as “uvm_test_top.env.ag1” only. Here for your reference.

set_config_object(“uvm_test_top.env.ag1”, “wiff”, wif,0);

I have created the object for agent in environment module. So I have set the hierarchy path of agent in top module.

Environment code:
****************
class tc_fifo_env extends uvm_env;

`uvm_component_utils(tc_fifo_env)
  tc_fifo_agent ag1;

function new(string name = "tc_fifo_env", uvm_component parent = null);
        super.new(name, parent);
        ag1 = new();
endfunction

 function void build_phase(uvm_phase phase);
        super.build_phase(phase);
        uvm_report_info(get_full_name(),"Build", UVM_LOW);
        ag1 = tc_fifo_agent::type_id::create("ag1",this);   
 endfunction

endclass

Testcase
**********
class parent_test extends uvm_test;
virtual intf intf_0;
  tc_fifo_env env;

`uvm_component_utils(parent_test)

function new (string name = "parent_test" , uvm_component parent = null);
  super.new(name , parent);
//  env = new ("env" , this);
endfunction

function void connect_phase(uvm_phase phase);
  uvm_top.print_topology();
endfunction

function void build_phase(uvm_phase phase);
  super.build_phase(phase);
     env = tc_fifo_env::type_id::create("env",this);
   set_config_int("env.ag1","is_active" ,0);
endfunction

endclass
8

In reply to MasilamaniRaja:

Hi ,

I have used uvm_config_db instead of set_config_* and get_config_* the fatal error is gone now.

Now I got another fatal message is

" UVM_FATAL @ 0: reporter@@seq01 [SEQ] neither the item’s sequencer nor dedicated sequencer has been supplied to start item in seq01 ".

In my agent file I have set uvm_active_passive_enum is_active = UVM_ACTIVE. But I have seen the output factory its showing UVM_PASSIVE.

Please help me.

Thanks & Regards,
P.Masilamani Raja

9

Hi

I got the Illegal virtual interface dereference in my monitor module.

Monitor:

class fifo_monitor extends uvm_monitor;

protected virtual interface intf intf_m;

protected tc_instruction txn_collect;

`uvm_component_utils (fifo_monitor)

function new (string name = “fifo_monitor” , uvm_component parent = null);
super.new(name , parent);
txn_collect = new();
endfunction

function void assign_vi (
virtual interface intf intf_1 );
intf_m = intf_1;

endfunction

task run ();
fork
collect_txn();
join
endtask

virtual protected task collect_txn();
forever
begin
@(intf_m.cb);
case (intf_m.read_write_control)
1’b1: txn_collect.rd_wr = WR;
1’b0: txn_collect.rd_wr = RD;
endcase

  @(intf_m.cb);

  txn_collect.data_in = intf_m.data_out;

end
endtask
endclass

“cb” is modport name.

clocking cb @(posedge clock);

output read_write_control,reset;
output data_in;
input data_out,full,empty;

endclocking

modport dut (input read_write_control,reset,data_in ,output full,empty,data_out);
modport tb (clocking cb);

Please help to resolve this issue.

10

you ave ag1 = new() and later have create method. is it a typo?

11

No…, First i have created the handle (ag1 = new ()) after that only created the method.

12

Hi

I have tried to force consecutive WR / RD operation in my sequence.

But I am getting the error message.

../tests/sequence.sv(20): randomize() failed due to conflicts between the following constraints:

../tests/sequence.sv(20): 1’h0;

UVM_WARNING ../tests/sequence.sv(20) @ 25: uvm_test_top.env.ag1.sequencer@@seq01 [RNDFLD] Randomization failed in uvm_do_with action

Sequence:

tc_instruction pkt; ---------- > Transaction file name

virtual task body();
begin
repeat(10) begin
uvm_do_with ( pkt , { pkt.rd_wr == WR ; pkt.data_in == data_in;} ) uvm_do_with ( pkt , { pkt.rd_wr == RD ;} ) ---------------- Line no : 20
end
end
endtask

Please help me ASAP.