you can call register reads and writes from any component. You have to set up the reg model correctly and pass the handle to the component. My guess is the register model is not fully set up correctly (either you don’t have a handle to the reg model or there is an incorrect setting with respect to the predictor, adapter, sequencer, etc… ). In my opinion, the Monitor is an odd place to perform a front door write.
I am trying to read a UVM Register from run_phase of UVM_Monitor and getting the following error
Error-[IOUCM] Illegal use of class method
dmtcomplex_uvc_pkg, “uvm_pkg::\uvm_reg::read (this.m_dmtcomplex_uvc.m_dmt_reg_block.dmt.dmtint, \this .status, this.intr_occurred, /* path = UVM_DEFAULT_PATH /, / map = null /, / parent = null /, / prior = (-1) /, / extension = null /, / fname = “\000” /, / lineno = 0 */);”
Class methods can’t be used in the current context.
Please check LRM for class method usage.
Please let me know if I can call UVM register read or write method from uvm_monitor
The monitor is by intention a passive component, i.e. no activity will be started from this component. This includes also register calls. If you setup your UVM environment correctly you can initiate any register activity through the sequencer/driver. And you can provide any register related data for further processing from the driver.
May I ask what is the solution for the TB issue? I am working on a similar case, which is trying to call read_reg inside a BFM which is a uvm_component. But getting same error.
I believe you have an architectural problem. Why are you doing simplke things complicated?.
read_reg should be executed always from a sequence and not from a BFM/driver.
In reply to chr_sue:
The component is more like a controller/host. Which needs to have some knowledge of the registers.
I was trying do to something like this. m_reg_seq.read_reg(register). It is when the compile error pop out. Even encapsulate the read_reg inside the sequence. I won’t be able to get the register value out of the sequence.
A monitor is a bad place to perform a read. The monitor is a passive component, having only inputs and never initiate something. It is more easy to have a read in the driver or in some other place like a scoreboard.
How do you deal with the register model? Please show some code.
The read_reg was implemented inside the driver/BFM. Not inside the monitor.
Register model wasn’t set up by me. But the base register access sequence has instantiated inside the base register sequence.
My question would be what RAL issue might be causing this compilation error.
Here is the code I am trying to use:
rm_base_req = rm_base_seq::type_id::create(“rm_base_req”); rm_base_req.read_reg(reg,status,val);
rm_base_seq is extended from uvm_reg_sequence. And this read_reg is the API Provided by the uvm_reg_sequence
read_reg
virtual task read_reg( input uvm_reg rg,
output uvm_status_e status,
output uvm_reg_data_t value,
input uvm_path_e path = UVM_DEFAULT_PATH,
input uvm_reg_map map = null,
input int prior = -1,
input uvm_object extension = null,
input string fname = “”,
input int lineno = 0 )
Reads the given register rg using uvm_reg::read, supplying ‘this’ as the parent argument.
rm_base_req.read_reg(reg,status,val);
reg: the register inside the reg_model. absolute path to the register inside the reg_model
status:uvm_reg_status
val:32bits wide logic
reg should be something like this: model.regA.
BTW there is no absolute path to the register model becaus ethe reg_model does not belong to the testbench hierarchy.
I’m having difficulty understanding your English, so in general, it’s best to post your code. I have done something similar to what you are trying, but I didn’t use a sequence. I just passed the reg_model handle into the component and used ‘peek’ (a backdoor read the registers). I don’t know if the method I used is ‘standard’ methodology or not. If you are only doing reads, here is another posting that discusses this: