I am trying to read a UVM Register from run_phase of UVM_Monitor and getting the following error Error-[IOUCM] Illegal use of class method dmtcomplex_uvc_pkg, “uvm_pkg::\uvm_reg::read (this.m_dmtcomplex_uvc.m_dmt_reg_block.dmt.dmtint, \this .status, this.intr_occurred, /* path = UVM_DEFAULT_PATH /…

In reply to chr_sue : The component is more like a controller/host. Which needs to have some knowledge of the registers. I was trying do to something like this. m_reg_seq.read_reg(register). It is when the compile error pop out. Even encapsulate the read_reg inside the sequence. I won’t be able to …

In reply to zhehuixu_intel : A monitor is a bad place to perform a read. The monitor is a passive component, having only inputs and never initiate something. It is more easy to have a read in the driver or in some other place like a scoreboard. How do you deal with the register model? Please show s…

In reply to chr_sue : The read_reg was implemented inside the driver/BFM. Not inside the monitor. Register model wasn’t set up by me. But the base register access sequence has instantiated inside the base register sequence. My question would be what RAL issue might be causing this compilation erro…

In reply to zhehuixu_intel : The question is what is ‘read_reg’. The access to a register follows this structure: reg_model_name.reg_map.reg You should show the piece of monitor code which contains the register access and the accurate compile error.

In reply to chr_sue : Here is the code I am trying to use: rm_base_req = rm_base_seq::type_id::create(“rm_base_req”); rm_base_req.read_reg(reg,status,val); rm_base_seq is extended from uvm_reg_sequence. And this read_reg is the API Provided by the uvm_reg_sequence read_reg virtual task re…

In reply to chr_sue : rm_base_req.read_reg(reg,status,val); reg: the register inside the reg_model. absolute path to the register inside the reg_model status:uvm_reg_status val:32bits wide logic

In reply to zhehuixu_intel : reg should be something like this: model.regA. BTW there is no absolute path to the register model becaus ethe reg_model does not belong to the testbench hierarchy.

In reply to chr_sue : I am positive the parameter was passed to the function correctly. Since it has been used at inside sequence. Just need to some light on how can I use the function inside the uvm_component

In reply to zhehuixu_intel : Dou you really pass the reg_model object to the sequence? You did not show the compile error message so far.

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Uvm reg read from uvm-monitor

UVM

chr_sue November 19, 2019, 9:01pm 15

In reply to zhehuixu_intel:

What are your actual parameters you are using when calling read_reg?