In reply to xdwzh:
It is possible to call register model methods from components if the component has the reg model handle and the register model is set up correctly.
May I ask what is the solution for the TB issue? I am working on a similar case, which is trying to call read_reg inside a BFM which is a uvm_component. But getting same error.
In reply to zhehuixu_intel:
I believe you have an architectural problem. Why are you doing simplke things complicated?.
read_reg should be executed always from a sequence and not from a BFM/driver.
In reply to chr_sue:
The component is more like a controller/host. Which needs to have some knowledge of the registers.
I was trying do to something like this. m_reg_seq.read_reg(register). It is when the compile error pop out. Even encapsulate the read_reg inside the sequence. I won’t be able to get the register value out of the sequence.
In reply to zhehuixu_intel:
A monitor is a bad place to perform a read. The monitor is a passive component, having only inputs and never initiate something. It is more easy to have a read in the driver or in some other place like a scoreboard.
How do you deal with the register model? Please show some code.
In reply to chr_sue:
The read_reg was implemented inside the driver/BFM. Not inside the monitor.
Register model wasn’t set up by me. But the base register access sequence has instantiated inside the base register sequence.
My question would be what RAL issue might be causing this compilation error.
In reply to zhehuixu_intel:
The question is what is ‘read_reg’. The access to a register follows this structure:
reg_model_name.reg_map.reg
You should show the piece of monitor code which contains the register access and the accurate compile error.
In reply to chr_sue:
Here is the code I am trying to use:
rm_base_req = rm_base_seq::type_id::create(“rm_base_req”); rm_base_req.read_reg(reg,status,val);
rm_base_seq is extended from uvm_reg_sequence. And this read_reg is the API Provided by the uvm_reg_sequence
read_reg
virtual task read_reg( input uvm_reg rg,
output uvm_status_e status,
output uvm_reg_data_t value,
input uvm_path_e path = UVM_DEFAULT_PATH,
input uvm_reg_map map = null,
input int prior = -1,
input uvm_object extension = null,
input string fname = “”,
input int lineno = 0 )
Reads the given register rg using uvm_reg::read, supplying ‘this’ as the parent argument.
In reply to chr_sue:
rm_base_req.read_reg(reg,status,val);
reg: the register inside the reg_model. absolute path to the register inside the reg_model
status:uvm_reg_status
val:32bits wide logic
In reply to zhehuixu_intel:
reg should be something like this: model.regA.
BTW there is no absolute path to the register model becaus ethe reg_model does not belong to the testbench hierarchy.
In reply to chr_sue:
I am positive the parameter was passed to the function correctly. Since it has been used at inside sequence.
Just need to some light on how can I use the function inside the uvm_component
In reply to zhehuixu_intel:
Dou you really pass the reg_model object to the sequence?
You did not show the compile error message so far.
In reply to zhehuixu_intel:
I’m having difficulty understanding your English, so in general, it’s best to post your code. I have done something similar to what you are trying, but I didn’t use a sequence. I just passed the reg_model handle into the component and used ‘peek’ (a backdoor read the registers). I don’t know if the method I used is ‘standard’ methodology or not. If you are only doing reads, here is another posting that discusses this:
In reply to dhserfer:
You can have a reg_model handle in any object including uvm_compnents. A typical example for this approach is a scoreboard which compares values depending on a register content. In this scenario you do not need to perform a backdoor por frontdoor access. Simply perform a get on the register to get the actual content of that register.
In reply to chr_sue:
I am also facing the same issue when using the ral model for read the register in my uvm_monitor am getting an error:
Error-[IOUCM] Illegal use of class method
/$PROJ_DIR/hxtop_interrupt_monitor.sv
Though as of nowam using ral model in my TB and all the registers sequences are working fine.
Can you please suggest me wat go wrong here?
In reply to yuvraj khare:
Could you please show some more code from your monitor?
And I’d like to ask you what are you doing with the read register value in the monitor?
In reply to chr_sue:
In reply to yuvraj khare:
Could you please show some more code from your monitor?
And I’d like to ask you what are you doing with the read register value in the monitor?
Basically it is Interrupt monitor, so am reading the status of interrupt (if interrupt is mask) i.e. using RAL model
if(top_cfg.interrupt_mask != 32’h0) begin
while(interrupt_status == 0) begin
regmodel.reg_bank.REG_ISR.read(status,interrupt_status);
end
Getting an error where am using the reg model.
Please let me know!
In reply to yuvraj khare:
If possible show the entire code, it is very difficult to figure out what is going wrong with just 2 lines of code.