Report phase

Hello I am running test and my question is end_of_elaboration phase prints the topology informaion but report phase is not working, below
is my program…

	virtual function void end_of_elaboration();
        	print();
 `uvm_info(get_type_name(), "----------TEST PASS------------------", UVM_NONE)

 	endfunction

	function void report_phase(uvm_phase phase);
   		uvm_report_server svr;
   		super.report_phase(phase);
    		svr = uvm_report_server::get_server();
   //`uvm_info(get_type_name(), "----------TEST PASS------------------", UVM_NONE)

	if(svr.get_severity_count(UVM_FATAL)+svr.get_severity_count(UVM_ERROR)>0) 
		begin
     			`uvm_info(get_type_name(), "---------------------------------------", UVM_NONE)
     			`uvm_info(get_type_name(), "----            TEST FAIL          ----", UVM_NONE)
     			`uvm_info(get_type_name(), "---------------------------------------", UVM_NONE)
    		end
    	else 
		begin
     			`uvm_info(get_type_name(), "---------------------------------------", UVM_NONE)
     			`uvm_info(get_type_name(), "----           TEST PASS           ----", UVM_NONE)
     			`uvm_info(get_type_name(), "---------------------------------------", UVM_NONE)
    		end
  	endfunction 

In reply to keshav_chokshi:

It is useless to print simulation results in the end_of_elaboration_phase, because the simulation hasn’t startexd yet.
Did your simulation reach the report_phase? This will be indicated automatically in your simulation log-file.

In reply to chr_sue:

In reply to keshav_chokshi:
It is useless to print simulation results in the end_of_elaboration_phase, because the simulation hasn’t startexd yet.
Did your simulation reach the report_phase? This will be indicated automatically in your simulation log-file.

I am new user can you tell me whare can i see simulation log file ?

In reply to keshav_chokshi:

You should see 2 things at the end of your simulation:

(1) — UVM Report Summary —
(2) a message like this: reporter [TEST_DONE] ‘run’ phase is ready to proceed to the ‘extract’ phase

please check if you have UVM_MAX_QUIT_COUNT set, does your test have any UVM_ERROR/FATAL ?

if the test exits with UVM_EXIT ( on FATAL or if quit count is reached ) , the report_phase is not executed, so what you are trying to do here wont work if your test exits with UVM_EXIT.

if you want to print any information, when tests encounters UVM_EXIT, only function to use is pre_abort ( in uvm_component )


 // Function: pre_abort
  //
  // This callback is executed when the message system is executing a
  // <UVM_EXIT> action. The exit action causes an immediate termination of
  // the simulation, but the pre_abort callback hook gives components an 
  // opportunity to provide additional information to the user before
  // the termination happens. For example, a test may want to executed
  // the report function of a particular component even when an error
  // condition has happened to force a premature termination you would
  // write a function like:
  //
  //| function void mycomponent::pre_abort();
  //|   report();
  //| endfunction
  //
  // The pre_abort() callback hooks are called in a bottom-up fashion.

or you can use final_block in a module.

In reply to sohan_b:

Would you guys know of a reason why pre_abort isnt getting called with UVM_TIMEOUT expires?

In reply to sharatk:

When timeout expeires you might not have any UVM_ERROR. In this case you have a tsructural problem. Your simulation might hang or it runs in an infinite loop. The question for UVM_ERROR is not relevant in this case.
Per definition pre_abort is only execuetd on UVM_EXIT and this depends on your parameter UVM_MAX_QUIT_COUNT.

In reply to chr_sue:

Can you please explain. I see an infinite loop.

668195000: !e[31mUVM_ERRORe[0m! [e[36muvm_test_top.env.LLC_SCBe[0m] e[31mrdAddrQ is not emptye[0m (/project/freya/fba/design/sharatk/dv_0/fbsource/fbcode/infra_asic_fpga/ip/fb_inference/dv/fb_inf_llc/gen/…/env/fb_inf_llc_sb_ext.sv:1421)
668195000: [uvm_test_top.env.LLC_SCB] Calling pre-abort
668195000: [uvm_test_top.env.LLC_SCB] In Check-Phase
668195000: [uvm_test_top.env.LLC_SCB] check_phase rdAddrQ. Addr-a0ea92340 ID-0 LEN-1
668195000: !e[31mUVM_ERRORe[0m! [e[36muvm_test_top.env.LLC_SCBe[0m] e[31mrdAddrQ is not emptye[0m (/project/freya/fba/design/sharatk/dv_0/fbsource/fbcode/infra_asic_fpga/ip/fb_inference/dv/fb_inf_llc/gen/…/env/fb_inf_llc_sb_ext.sv:1421)
668195000: [uvm_test_top.env.LLC_SCB] Calling pre-abort
668195000: [uvm_test_top.env.LLC_SCB] In Check-Phase
668195000: [uvm_test_top.env.LLC_SCB] check_phase rdAddrQ. Addr-a0ea92340 ID-0 LEN-1

This is my function

virtual function void pre_abort();
`uvm_info(get_full_name, “Calling pre-abort”, UVM_NONE )
check_phase(null);
endfunction

My quit_coiut is set as 1.

In reply to sharatk:

For the method check_phase():
The uvm_check_phase phase implementation method.
This method should never be called directly.

Do you see the above data only twice or more than twice?

In reply to chr_sue:
The main reason to implement pre_abort was if the test is being killed by UVM_TIMEOUT, it never calls post-run phases.
So thats why I put check_phase inside pre_abort.

What I think is happening is. check_phase generates an UVM_ERROR. Because of max_error_count being 1, it exits and calls pre_abort, which again calls check and that calls pre_abort.
If this is true , then I think its a UVM bug.

In reply to sharatk:

Be careful with the bug.
You did not answer my 2nd question. Could you please do it now?

In reply to chr_sue:

Sorry about that. The test was stuck in an infinite loop and I saw those prints a lot of times.

In reply to sharatk:

OK, I bekieve you are hunting for something you could see implementing appropriate uvm_info and uvm_error in your testbench code.
Investigate this line of code.
668195000: ![31mUVM_ERROR[0m! [[36muvm_test_top.env.LLC_SCB[0m] [31mrdAddrQ is not empty[0m (/project/freya/fba/design/sharatk/dv_0/fbsource/fbcode/infra_asic_fpga/ip/fb_inference/dv/fb_inf_llc/gen/…/env/fb_inf_llc_sb_ext.sv:1421)
What are you doing here?