Verification Academy

Topic	Replies	Views	Activity
How are two tops (hvl_top and hdl_top) run in one simulation? UVM UVM , dual-top-modules	2	1131	August 25, 2022
If the UVM test which doesnt call the sequence but has objections , What happens to a UVM_driver waiting on a request? UVM UVM	1	341	August 25, 2022
Iteration Order for Class Indexes of Associative Array SystemVerilog SystemVerilog , Iteration-Order-for-Class-Indexes-of-Associative-Array	4	948	August 24, 2022
With clause error Coverage Coverage	3	1091	August 24, 2022
Writing into memory and reading from memory SystemVerilog SystemVerilog , System-Verilog , read-write-task	9	4083	August 24, 2022
Constraint existence of value into an array SystemVerilog SystemVerilog , constraint , randomization , array-methods , arrays	6	4382	August 24, 2022
Calling verilog code from class in uvm UVM UVM	5	1006	August 24, 2022
Ralgen mapping register into ralf file UVM UVM , ip-xact , RAL-IPXACT , ralgen-in-VCS	0	1007	August 24, 2022
MATLAB and UVM RAL UVM UVM , matlab	0	398	August 24, 2022
Randomization of multiple of N SystemVerilog SystemVerilog , constraint-randomization , randomization	2	1117	August 24, 2022
Questions on alu generator user guide UVM UVM	3	598	August 24, 2022
Using MATLAB generated models in SystemVerilog testbenches UVM UVM	1	522	August 23, 2022
Cross coverage with an array SystemVerilog SystemVerilog , Coverage , array-bins , cross-bins	5	1360	August 23, 2022
How to pass parameter value from class to module UVM UVM , How-to-pass-parameter-value-from-Class-To-Module	5	797	August 23, 2022
Write the sv driver code to generate and drive 'valid' from TB side so that it follows the below -mentioned protocol and conditions. please note that there is no transaction or packet given here SystemVerilog SystemVerilog , SVA , Assertions-clock	1	1004	August 22, 2022
Extend task: main_phase in extended test class, members of the base task are not visiable UVM UVM	3	714	August 22, 2022
The 'with' in streaming dynamically sized data is giving error (11.4.14.4 of LRM(1800-2017)) SystemVerilog SystemVerilog , streaming-operators	4	692	August 22, 2022
How to implement delay in uvm reg callback? UVM UVM , UVM-callback , uvm_reg_cbs	0	435	August 22, 2022
What is the best/recommended practice to implement a bi-direction bus in uvm framework UVM UVM , UVM-Framework	1	562	August 22, 2022
How to check signal(ex: ack) is high between time(min time and max time) using among assertions or constraints or uvm macros UVM UVM , assertion , sv-assertion	0	435	August 22, 2022
What's the benefit to separate alu in/out agent? UVM UVM , uvm-framework-alu	2	603	August 22, 2022
Effects of type_option.merge_instances=1 on Functional and Code Coverage SystemVerilog SystemVerilog , Effects-of-type_optionmerge_instances1-on-Functional-and-Code-Coverage	3	1573	August 21, 2022
Asynchronous FIFO Multithreaded assertion SystemVerilog SystemVerilog , assertion , SVA	7	2809	August 21, 2022
Popular tools for tracking regression Coverage Coverage	1	365	August 21, 2022
Parameterized Covergroup V/S Overriding function sample() Coverage Coverage , Parameterized-Covergroup-VS-Overriding-function-sample	4	2789	August 19, 2022
How do I define an associative array of queues? SystemVerilog SystemVerilog , associative-array , Queues-in-system-verilog , systemverilog-Arrays	15	16262	August 19, 2022
Regarding connecting Interface to RTL and RTL to Interface UVM UVM , systemverilog-uvm	1	858	August 19, 2022
Driving internal signal of DUT from uvm driver UVM UVM , force-release-behavior , systemverilog-driver-monitor-virtual-interface-transaction	1	635	August 19, 2022
How to find, if register model is updated or not UVM UVM , RAL	0	417	August 19, 2022
Read Operation (Reading From Memory) SystemVerilog SystemVerilog , System-Verilog , read-operation	1	780	August 18, 2022