Verification Academy

Topic	Replies	Views	Activity
SystemVerilog property with a real datatype input argument SystemVerilog SystemVerilog	3	2079	March 18, 2022
What is the downside of implementing interrupt service routine in a component? UVM UVM , uvm_event , ISR	2	726	March 18, 2022
Are class object handles passed by reference when used are class method arguments? SystemVerilog SystemVerilog	3	1359	March 18, 2022
Reactive agent for memory storage UVM UVM , sequence , reactive-agent	11	3844	March 18, 2022
Is it good to save svOpenArrayHandle for later usage? SystemVerilog SystemVerilog	5	1017	March 18, 2022
Multiple maps to predictor UVM UVM , UVM-RAL-UVM	0	689	March 18, 2022
How to execute specific sequence in virtual sequence? UVM UVM , systemverilog-uvm , virtual-sequence-virtual-sequencer	4	1719	March 17, 2022
System Verilog Concurrent Assertions SystemVerilog SystemVerilog , SVA	6	1906	March 17, 2022
Connecting multiple agents UVM UVM , systemverilog-uvm	0	615	March 17, 2022
How to call the user_defined callback class from a sequence? UVM UVM	0	652	March 17, 2022
Lint warning on conditional expression is statically evaluated to false SystemVerilog SystemVerilog	2	799	March 17, 2022
Uvm_seq_item_pull_port and uvm_blocking_put_port UVM UVM , base_test-uvm_tlm_fifo	1	1484	March 16, 2022
Finding 0 coverage in TOP registers on firing regression Coverage Coverage	1	551	March 16, 2022
Unable to compile a register model using registers of size 2048 bits UVM UVM , questasim , UVM-Questa , uvm-register-model	12	2467	March 16, 2022
SVA : question on using throught vs [*n] SystemVerilog SystemVerilog , assertion , SVA	4	996	March 15, 2022
UVM scoreboard implementation UVM UVM , base_test-uvm_tlm_fifo	1	747	March 15, 2022
Inline constraints using randomize() -with to set "x" on an integer throws compile error SystemVerilog SystemVerilog , constraint-randomization	1	521	March 14, 2022
I followed the steps to create RAL but it fails when debugging UVM UVM	1	763	March 14, 2022
Question on Array.Sum() Method , generate a n*n matrix such that there is only one 1's in a coloumn SystemVerilog SystemVerilog , constraint-randomization , systemverilog-Arrays	8	1572	March 14, 2022
Achieving Unique Array via inside operator SystemVerilog SystemVerilog , Achieving-Unique-Array-via-inside-operator	5	1029	March 14, 2022
MATLAB integration with SV UVM UVM , Cookbook-MatlabIntegration	1	648	March 14, 2022
Multiple named event in one forever loop SystemVerilog SystemVerilog , Named-events , triggered	2	1152	March 14, 2022
How to initial the dynamic array with struct SystemVerilog SystemVerilog	2	1741	March 12, 2022
Property VS Sequence in Sensitivity List SystemVerilog SystemVerilog , Property-VS-Sequence-in-Sensitivity-List	1	736	March 12, 2022
How to display time in femtoseconds for uvm_info statements UVM UVM , UVM_VERBOSITY , timescale-uvm_info	5	3312	March 12, 2022
Constraint on at least N unique digits in array SystemVerilog SystemVerilog , constraint-randomization	8	1371	March 12, 2022
Queue constraint SystemVerilog SystemVerilog , constraint-on-queue	2	984	March 12, 2022
Function call returns bad sum result SystemVerilog SystemVerilog	2	525	March 11, 2022
How to use variable for forcing the path SystemVerilog SystemVerilog , systemverilog-Arrays	4	1345	March 11, 2022
Sending whether an agent is active or passive via config db to a spesific component UVM UVM , uvm_config_db	5	2020	March 11, 2022