Multiple named event in one forever loop

SystemVerilog
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1

When we write Verilog code that takes multiple events in one always block, the code is like Code0, shown below. I want to do the same thing in SystemVerilog using named events and tried to write “Code1”. Are there any problems in “Code1”? ( It worked as expected, but I do not have confidence in the code because I could not find such examples in LRM nor google search…)

In code1, the forever loop is blocked by multiple events(ev_001 and ev_002), and when unblocked, the different operation takes place depending on the triggered event.

[Code0(Verilog)]


 bit ev_001, ev_002;
   always @(ev_001 or ev_002) begin
      if(ev_01)
        out = 1;
      if(ev_02)
        out = 2;
   end

[Code1(SystemVerilog)]

module tb();
   event ev_001;
   event ev_002;
initial begin
      forever begin
         @(ev_001 or ev_002);
         if(ev_001.triggered)
           $display("001 event triggered @%t", $time);
         if(ev_002.triggered)
           $display("002 event triggered @%t", $time);           
      end
end
endmodule

Regards

2

In reply to tsb_matumoto:

The reason you do not see many examples using named events is because they are very difficult for most people to understand without deep knowledge of SystemVerilog scheduling semantics.

The problem with this code is if you trigger ev_001, the first $display executes and then later in the same time step you trigger ev_002, then the first $display executes a second time. You would need to make sure that double execution would not be a problem.

3

In reply to dave_59:

Thank you very much.
I got the problem of multiple trigger for ev_001.
Regards,