Property VS Sequence in Sensitivity List

SystemVerilog
,
1

Hi all ,

I am trying various sample code to note differences between property and sequence

I have the following code ::


module  top ;

 bit  req , gnt , clk ;


`ifdef  PROP
  property  sr1 ;
`else
  sequence  sr1 ;
`endif

      @( posedge clk )   req  ##2  gnt ;   

`ifdef  PROP
   endproperty 
`else
   endsequence
`endif


  always @ ( sr1 )   $display(" TIME:%0t  Assertion  PASS " , $time ) ;   

  initial  forever #5 clk = ! clk ;

   initial  begin

     #4 ; req = 1 ;

    #20 ; gnt = 1 ;

    #2 ;
    $finish() ;

  end

endmodule

For +define+PROP , I observe that Simulator1 throws a Compilation error whereas it isn’t so with Simulator2 .

Although Simulator2 doesn’t report anything i.e No Pass report .

For No +define the O/P is same across both Simulators :: TIME:25 Assertion PASS

[ Q ] My question is whether it’s valid to use a property in sensitivity list as per LRM ?

2

In reply to hisingh:

Sequences generate an event upon upon reaching an endpoint and may be used in an event control (a.k.a. sensitivity list).

Properties are either true or false and cannot be used in an event control. Interestingly 2 tools on EDAPlayground correctly have a compiler error, and 2 tools never trigger the event control.

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