Verification Academy

Topic	Replies	Views	Activity
How to disable a bins SystemVerilog SystemVerilog	1	1171	April 2, 2022
Get_event_pool usage UVM UVM , UVM-system-verilog , configdb , get_event_pool	7	9246	April 1, 2022
Dist constraint error SystemVerilog SystemVerilog	1	360	April 1, 2022
Why need dynamic array SystemVerilog SystemVerilog , why-need-dynamic-array-in-SV	9	9000	April 1, 2022
Register sequence error UVM UVM	13	1268	April 1, 2022
Extern function/task definition in generate-block scope within scope of class definition SystemVerilog SystemVerilog , extern-task-of-a-class	4	814	April 1, 2022
Regarding constraint overlap SystemVerilog SystemVerilog , constraint-randomization	2	868	March 31, 2022
If condition statement UVM UVM , if-condition	8	1876	March 31, 2022
Coverage increment Coverage Coverage	5	843	March 31, 2022
Regarding Vacuous Pass Reports SystemVerilog SystemVerilog , Regarding-Vacuous-Pass-Reports	2	632	March 30, 2022
Constraint array index cyclic unsolvable error SystemVerilog SystemVerilog , systemverilog-constraint	1	709	March 30, 2022
Randomize a two-dimensional array with unique elements SystemVerilog SystemVerilog , dynamic-array-constraint	2	1852	March 30, 2022
Pulse generator Task SystemVerilog SystemVerilog , testbench , pulsecounter	1	981	March 30, 2022
Case statement inside constraint UVM UVM , uvm-sv-constraints	5	3786	March 29, 2022
How to access structures element using index SystemVerilog SystemVerilog , sysyem-verilog	4	2290	March 29, 2022
Chandle and SV byte array SystemVerilog SystemVerilog , chandle-casting	1	1022	March 29, 2022
Using .matched with Out of Phase Clocks SystemVerilog SystemVerilog , Using-matched-with-Out-of-Phase-Clocks	3	745	March 29, 2022
Assertion on arbiter SystemVerilog SystemVerilog	1	1334	March 28, 2022
Signal starts in the middle of the clock SystemVerilog SystemVerilog	8	1369	March 28, 2022
Round Robin Assertion SystemVerilog SystemVerilog	2	432	March 28, 2022
Test Fail for Random Seed UVM UVM , Random-seed-fail	1	792	March 28, 2022
ReadID related Assertion SystemVerilog SystemVerilog , ReadID-related-Assertion	2	619	March 27, 2022
Passing string name as input to macro but internally it represents the actual value. Is that Possible? UVM UVM , compilation-macro	2	1837	March 27, 2022
How to generate same random data across 2 sequences UVM UVM , virtual-sequence-sequence_item	2	936	March 27, 2022
Assign dynamic width SystemVerilog SystemVerilog	1	811	March 26, 2022
SVA evaluation SystemVerilog SystemVerilog	12	6585	March 25, 2022
Why does uvm_reg_map not always set a parent? Doesn't this prevent it from cleaning after itself when it performs a write/read? UVM UVM	1	485	March 25, 2022
Signals not being driven after binding to interface UVM UVM , --Error-vsim-8343-tbdriversv169-Clocking-block-output-vife_ifcbRREADY-is-not-legal--for-the-left-hand-side-of-this-or-another-expression	1	533	March 25, 2022
UVMF without Questa UVM UVM	2	787	March 25, 2022
Frequency to period conversion SystemVerilog SystemVerilog	1	1225	March 25, 2022