Signals not being driven after binding to interface

UVM
,
1

RTL doesnt have a systemverilog interface defined. In the TB TOP , i bind the TB interface to the DUT and use that in the config_db to pass to the rest of the environment. However the signals are seeing an x . Do i need to do assigns of each of the interface signals to the TB signals , after binding? The sequences are driving the interface signals directly . So i expected to not have Assigns in the tb_top and use the bind interface itself to drive the signals.

module tb_top ( RTL signals )

bind DUT intf intf_inst(.*);

initial begin
    uvm_config_db#(virtual intf):: set("","", "intf", intf_inst);

end
endmodule

class base_test extends uvm_test;
    < uvm_config_db gets the interface>
    intf.reset <= 1;  // I expect this to drive the signals at the interface level. I do not see this.


endclass
2

In reply to dsherlek:

Without seeing your DUT and intf declarations, it’s hard to explain exactly why you are seeing X’s. But a better approach is connecting the ports of your DUT to interface signals directly.

module DUT(input clk, rst, inout data);
  ...
endmodule
interface intf;
  logic clk, rst;
  wire data; 
endinterface

module tb_top;

   intf i();
   DUT DUT_inst(i.clk, i.rst, i.data);

endmodule

This is explain in more detail in my DVCon paper: The Missing Link: The Testbench to DUT Connection