Dist constraint error

SystemVerilog
1

hi actually i am facing a problem in dist connstraint in the below code i am getting value only from one range that is bigger one.


class packet;
  rand bit [47:0] addr;

  constraint addr_range { addr dist { [48'h0:48'h110]:= 10,[48'h111:48'hFFE]:= 8,[48'h10000111:48'h10000FFE]:= 5,[48'h10000FFF:48'h20000FFF]:=5 }; }
endclass

module constr_dist;
  initial begin
    packet pkt;
    pkt = new();
    $display("------------------------------------");
    for(int i=0;i<10;i++) begin
      pkt.randomize();
      $display("\taddr = %0h",pkt.addr);
    end
    $display("------------------------------------");
  end
endmodule

The result am getting are
addr = 1eaf5a25
addr = 1b4baadc
addr = 107ec560
addr = 1131a4c6
addr = 1ad74c04
addr = 1bd9f916
addr = 142b8384
addr = 1db82a6f
addr = 10a628ef
addr = 1e173e05
what the wrong i am doing i did not figure out.

2

In reply to Jaygupta:

You need to apply the weight to the range with :/ instead of each value in the range with :=.

Coincidentally, this is currently being clarified in the next revision on the IEEE 1800-2017 SystemVerilog LRM. When you use [range]:=weight, it effective gives length(range)*weight to that range.