Hello guys ,
I am writing register sequence class to write the value in DUT register fields .
if I am passing own value than testcase passed :-
regmodel.DLALR0.LA_31_LSB.write(.status)status) , .value (3'd5) ) ;
but according my requirement i would like to pass the value generated from our configuration class than its throughing ERROR.
regmodel.DLALR0.LA_31_LSB.write(.status)status) , .value (cfg.local_min_addr) ) ; // ERROR
//================ERROR MESSAGE =============================
Error-[ICTTFC] Incompatible complex type usage
/project/msgfeip_lfsl_verif_1/usr/shubham/ATU/ATU_FUNC/d_ip_atu_syn_tb/TESTBENCH/classes/seq_lib/d_ip_atu_initialization_seq_lib.sv, 89
Incompatible complex type usage in task or function call.
The following expression is incompatible with the formal parameter of the
task. The type of the actual is 'bit[48:0]$[]', while the type of the formal
is 'bit[63:0]'. Expression: this.cfg.local_min_addr
Source info: uvm_pkg::\uvm_reg_field::write (this.regmodel.DLALR0.LA31_LSB,
this.status, this.cfg.local_min_addr, /* path = UVM_DEFAULT_PATH */, /* map
= null */, /* paren ...
In reply to raj@123:
Unfortunately you do not show the definition of your configuraion class. But it seems there is a mismatch with respect to the data type for the write function and the data type in the configuration class (local_min_addr).
In reply to chr_sue:
In reply to raj@123:
Unfortunately you do not show the definition of your configuraion class. But it seems there is a mismatch with respect to the data type for the write function and the data type in the configuration class (local_min_addr).
//Declaration of local_min_addr in configuration class and sige of IF_AW = 49 bit (parameterized
rand bit [IF_AW-1:0] local_min_addr[]; //array of local lower address values
In reply to raj@123:
You want to assign a dynamic array local_min_addr of words with a width of 49 bits to a register of a certain width.
In reply to chr_sue:
can you share syntax of coding .
In reply to raj@123:
I do not know the width of the register. I guess it is 64 bits.Correct?
Then you could use
regmodel.DLALR0.LA_31_LSB.write(.status)status) , .value (cfg.local_min_addr[0]));
cfg.local_min_addr[0] is 1 ord with the width of 49 bits. It would be useful to use the same width as the register width is.
In reply to chr_sue:
In reply to raj@123:
I do not know the width of the register. I guess it is 64 bits.Correct?
Then you could use
regmodel.DLALR0.LA_31_LSB.write(.status)status) , .value (cfg.local_min_addr[0]));
cfg.local_min_addr[0] is 1 ord with the width of 49 bits. It would be useful to use the same width as the register width is.
Size of DLALR0 register is 32 bit , where [31:16] field stores local_min_addr while [15:0] is reserverd field .
regmodel.DLALR0.LA_31_LSB.write(.status)status) , .value (cfg.local_min_addr[0]));
after writing in above manner as per your statement showing one error
Error-[IPNA] Incorrect placement of named arguments
/project/classes/seq_lib/d_ip_atu_initialization_seq_lib.sv, 89
top_level_module, “.status(\this .status)”
Named arguments cannot be passed before positional arguments
4 warnings
1 error
In reply to chr_sue:
if writing like this testcase pass is it write way to write the value in register fields
regmodel.DLALR0.LA_31_LSB.write(status , cfg.local_min_addr[0]);
In reply to raj@123:
You did not say that you want to write only a register field. You have to consider this with respect to the data width.
And you have atypo here:
regmodel.DLALR0.LA_31_LSB.write(.status)status) , .value (cfg.local_min_addr[0]));
It should be
regmodel.DLALR0.LA_31_LSB.write(.status(status) , .value (cfg.local_min_addr[0]));
In reply to chr_sue:
Hii sir let me know what is incorrect in bellow read operation getting an error .
regmodel.DCR0_LOCK.read(.status(status) , .value(1) ); line no 170
Error-[AIORPML] Illegal argument to port
/project/classes/seq_lib/d_ip_atu_initialization_seq_lib.sv, 170
"uvm_pkg::\uvm_reg_field::read (this.regmodel.DCR0_LOCK, this.status, 1, /* path = UVM_DEFAULT_PATH */, /* map = null */, /* parent = null */, /* prior = (-1) */, /* extension = null */, /* fname = "\000" */, /* lineno = 0 */);"
Argument to inout/output/ref port must be an expression that is valid on the
left-hand side of a procedural assignment.
Argument: 1
Error-[IATOTC] Illegal argument to output of task call
/project/classes/seq_lib/d_ip_atu_initialization_seq_lib.sv, 170
"1"
Expression below cannot be connected to output of task call because it is
not a register or variable.
Expression: 1
Source info: uvm_pkg::\uvm_reg_field::read (this.regmodel.DCR0_LOCK,
this.status, 1, /* path = UVM_DEFAULT_PATH */, /* map = null */, /* parent =
null */, /* prior = (-1) ...
In reply to raj@123:
It is exactly this line:
regmodel.DCR0_LOCK.read(.status(status) , .value(1) );
You want to store the read value in ‘1’, which is definitely not a variable.
It should be like this
regmodel.DCR0_LOCK.read(.status(status) , .value(rd_value) );
rd_value has to be declared as the right data type.
In reply to chr_sue:
and we need to declear rd_value in sequence class in following manner .
class sequence extends uvm_reg_sequence ;
bit rd_value=1; // rd_value with 1 value
task body();
regmodel.DCR0_LOCK.read(.status(status) , .value(rd_value) );
endtask
endclass
is it correct
In reply to raj@123:
No this is not correct. It is useless to initialize this variable. It has to store the read data comming from the register. And this variable has to have the right width (the same as the register has).
It should look like this:
bit [REG_WIDTH-1:0] rd_value;
task body();
regmodel.DCR0_LOCK.read(.status(status) , .value(rd_value), .parent(this) );
endtask
In reply to chr_sue:
In reply to raj@123:
No this is not correct. It is useless to initialize this variable. It has to store the read data comming from the register. And this variable has to have the right width (the same as the register has).
It should look like this:
bit [REG_WIDTH-1:0] rd_value;
task body();
regmodel.DCR0_LOCK.read(.status(status) , .value(rd_value), .parent(this) );
endtask
Thanks sir