In DUT :
always@(posedge clk)begin
if(x)
Q<=1;
end
forever@(posedge clk) begin
if(x)
tx.Q=intf.Q;
end
In reply to shekher201778:
To answer your question, we need to know how X is assigned a value.
Two signal transitions can never happen exactly at the same moment—one has to come before the other. There are a number way of guaranteeing an ordering, the most basic is using the nonblocking assignment <=. There is a tremendous amount of material out on blocking versus non-blocking assignments(NBA). The basic premise is that SystemVerilog has two main event scheduling regions or queues; Active and NBA.
All statements execute in the Active region and NBA updates get scheduled in the NBA region as part of executing an assignment in the active region. All Active events execute until the queue is emptied. Then the NBA queue of updates becomes the Active queue and the process continues potentially adding more events to the Active and NBA queues for the current time slot or future times. This process repeats over and over again until the Active and NBA events are both empty. Then time can advance so a future time active queue becomes the current Active queue. In reality the are a few ore event regions, but if you understand the way these two operate you can quickly understand the others.
In reply to dave_59:
Thanks dave_59 for responding. In my case x is assigned using NBA exactly @posedge clk. So you means if x is assigned value using NBA, then it will be updated at the end of current time slot. But if condition is checked in the active region, so active region value of x i.e preponed value (which is 0 in my case) will be used in if condition. Updated value will be assigned in NBA region that comes after active region. That’s why if condition is evaluated false even though x is going 0 to 1 at posedge clk. If x is assigned using blocking or assign statement, then if condition will be evaluated true. Same rule applies to UVM monitor also.
Correct me if i am wrong.
In reply to shekher201778:
If x is assigned with a blocking assignment from another process also synchronized to the same clock edge, then you have a race condition
The same tules apply to the UVM code as long as the code starts from a initial block in a module.
module test;
initial uvm_pjg::run_test();
endmodule
If you start it in a program block (which we do not recommend), then things get much more complicated with the addition of more unnecessary event regions.
fork
forever @(posedge clk) begin
Q1 = D;
Q2 <= D;
end
forever @(posedge clk) begin
Q3 <= Q1; // race
Q4 <= Q2;
end
join
Regardless of whether this is UVM code or plain SystemVerilog, or in a module or program block, there will always be a race condition here. In the Q3 <= Q1 statement, the race is whether Q3 gets the old value of Q1 before the clock edge, or the updated value after the clock edge. The Q4 <= Q2 assignment always gets the old value of Q2; there is no race condition.
In reply to dave_59:
Hi dave_59. In the given code snippet, @ posedge clk10, Q1=D will be executed before Q3<=Q1 as blocking assignment is executed before NBA. So Q3 must get updated value of Q1. How can this be race condition ? Please correct me if i am wrong.
In reply to shekher201778:
Incorrect. The two assignment statements execute in any order. It’s only the update to the LHS of the NBA that gets scheduled after both statements have executed.
In reply to dave_59:
Thanks dave_59 for correcting me. Just one more thing i want to confirm. When NBA executes, it first evaluate RHS expression & store the new value in temporary storage & when NBA region occurs, this new value is assigned to LHS variable. So my question is does it uses preponed region value of RHS variable. for e.g
always@(posedge clk)
#1 a<=#5 b;
here, will the value of b in the preponed region of 1 ns is used ?
In reply to shekher201778:
It uses the value of the RHS expression in the active region. Whether the active region value of the expression is the same as the preponed region value depends on how b is assigned. If you have
always@(posedge clk)
#1ns a<=#5ns b;
always@(posedge clk)
#1ns b = b +1;
There is still a race between whether at 1ns after the posedge clock if the first assignment to a uses the old value of b (which would be the same value it had in the preponed region), or the new value of b that was just updated by the second assignment statement in the active region.
Certain constructs like assertions and clocking blocks only use values from the preponed region. This is called the sampled value.