In reply to shekher201778:
If x is assigned with a blocking assignment from another process also synchronized to the same clock edge, then you have a race condition
The same tules apply to the UVM code as long as the code starts from a initial block in a module.
module test;
initial uvm_pjg::run_test();
endmodule
If you start it in a program block (which we do not recommend), then things get much more complicated with the addition of more unnecessary event regions.
fork
forever @(posedge clk) begin
Q1 = D;
Q2 <= D;
end
forever @(posedge clk) begin
Q3 <= Q1; // race
Q4 <= Q2;
end
join
Regardless of whether this is UVM code or plain SystemVerilog, or in a module or program block, there will always be a race condition here. In the Q3 <= Q1 statement, the race is whether Q3 gets the old value of Q1 before the clock edge, or the updated value after the clock edge. The Q4 <= Q2 assignment always gets the old value of Q2; there is no race condition.