In reply to shekher201778:
To answer your question, we need to know how X is assigned a value.
Two signal transitions can never happen exactly at the same moment—one has to come before the other. There are a number way of guaranteeing an ordering, the most basic is using the nonblocking assignment <=. There is a tremendous amount of material out on blocking versus non-blocking assignments(NBA). The basic premise is that SystemVerilog has two main event scheduling regions or queues; Active and NBA.
All statements execute in the Active region and NBA updates get scheduled in the NBA region as part of executing an assignment in the active region. All Active events execute until the queue is emptied. Then the NBA queue of updates becomes the Active queue and the process continues potentially adding more events to the Active and NBA queues for the current time slot or future times. This process repeats over and over again until the Active and NBA events are both empty. Then time can advance so a future time active queue becomes the current Active queue. In reality the are a few ore event regions, but if you understand the way these two operate you can quickly understand the others.