Verification Academy

Topic	Replies	Views	Activity
Object-oriented Testbench SystemVerilog SystemVerilog , error , System-Verilog , UVM-Coverage , covergroup	1	579	August 18, 2022
Can we use a distribution on enum variable? SystemVerilog SystemVerilog	4	2460	August 18, 2022
Update problem UVM UVM	3	550	August 18, 2022
How to verify the Write 1 to clear register in RAL? UVM UVM	0	557	August 18, 2022
UVM_INFO dropping response for sequence 2, sequence not found. Probable cause: sequence exited or has been killed UVM UVM , uvm_info , sequencer	2	1058	August 18, 2022
Defining macro based on parameter value SystemVerilog SystemVerilog , System-Verilog	2	988	August 18, 2022
Duplicate values in Fixed bin SystemVerilog SystemVerilog , Duplicate-values-in-Fixed-bin	1	370	August 18, 2022
C model golden file and monitor data comparision UVM UVM , C-MODEL-GOLDEN-MODEL	2	471	August 17, 2022
How to write a constraint for xor gate? UVM UVM	5	2312	August 17, 2022
RUN_TIME_ERROR UVM UVM	0	386	August 17, 2022
Spy Interface SystemVerilog SystemVerilog , interface , FIFO-UVM-VIRTUAL-INTERFACE	2	768	August 17, 2022
Having instances of Both Child class and Parent class within a module SystemVerilog SystemVerilog , class , instantiation-vs-inheritance , chandle , extern-task-of-a-class	3	860	August 17, 2022
Constraint for random Memory access SystemVerilog SystemVerilog	3	553	August 16, 2022
XMRE in UVM 1.1 UVM UVM , test-uvm-coverage- , errorXMRE	2	859	August 16, 2022
Constraining the columns of a Matrix SystemVerilog SystemVerilog , constraint-randomization , constraint-foreach-loop	7	1156	August 16, 2022
[Formal verification] Is there a way to bind some assumption to a specific assertion to reduce the stimulus for only that assertion? SystemVerilog SystemVerilog , systemverilog-ASSERTION-bind	2	803	August 16, 2022
File parsing UVM UVM	1	483	August 16, 2022
HELP ME WITH THIS CODE SystemVerilog SystemVerilog , UVM , error , system_verilog	1	456	August 16, 2022
Task with arguments SystemVerilog SystemVerilog	1	418	August 16, 2022
Unable to verify these errors SystemVerilog SystemVerilog , error , class , supernew	3	1228	August 15, 2022
Constraints to set 32 bit address to be word aligned and 1Kb in length SystemVerilog SystemVerilog , System-Verilog , constraint-randomization	2	2040	August 15, 2022
Associative array of covergroups SystemVerilog SystemVerilog , Associative-array-of-covergroups	2	471	August 14, 2022
The best and most concise way to find the value of the last element in an associative array? SystemVerilog SystemVerilog , associative_arrays	4	2158	August 13, 2022
Queue sorting SystemVerilog SystemVerilog	7	7419	August 13, 2022
How to write a assertion to check if the clock is running before a bus or signal sees a change SystemVerilog SystemVerilog , assertion , Assertions-clock	3	794	August 12, 2022
A question concerning execution order of methods in a class/object SystemVerilog SystemVerilog	3	540	August 12, 2022
Triggering assertions from always block and passing arguments SystemVerilog SystemVerilog , SVA , OVL_SVA	3	736	August 12, 2022
Assign random delay to existing clock SystemVerilog SystemVerilog , systemverilog-clock-verilog	5	1504	August 11, 2022
UVM driver waiting for another signal from different interface UVM UVM , systemverilog-uvm	3	636	August 11, 2022
How to randomize delay and assign it to clock SystemVerilog SystemVerilog , constraint-randomization , 0-delays , systemverilog-clock-verilog	4	1026	August 10, 2022