I got the following message while the test is running:
UVM_INFO @ 2869937: uvm_test_top.uart_sa_env.uart_env.uart_agent.sequencer [Sequencer] Dropping response for sequence 2, sequence not found. Probable cause: sequence exited or has been killed
It’s a simple test which send only one item.
The relevant code in the test is:
virtual task run_phase( uvm_phase phase );
uvm_reg_data_t rx_data;
uvm_status_e status;
uart_wr_seq = uart_base_sequence::type_id::create("uart_wr_seq");
phase.raise_objection(this);
#100ns;
`uvm_info(get_type_name(), {"write 1 to sys cgf reg ", get_full_name()}, UVM_LOW);
m_ral_model.uartlcr_reg.write(status , 32'h209);
#10ns;
uart_wr_seq.start(uart_sa_env.uart_env.uart_agent.sequencer);
#5000ns;
m_ral_model.uartdr_reg.read(status, rx_data);
#10ns;
`uvm_info({get_type_name," : ID"},$psprintf("rx_data is %f:",m_ral_model.uartdr_reg.get()),UVM_HIGH)
$display("rx data is %f", rx_data);
`uvm_info({get_type_name," : ID"},$psprintf("rx_data is %f:",rx_data),UVM_HIGH)
//m_ral_model.uartdr_reg.write(status , 32'h1C);
//#5000ns;
//m_ral_model.uartdr_reg.write(status , 32'hFF);
endtask //run ghase
What can cause the sequencer to exited?
cgales
August 17, 2022, 3:31pm
2
In reply to Sarit8r :
It’s likely that the uart_wr_seq is operating in a different manner that the uart_driver. The sequence isn’t expecting a reply from the driver, so it finishes running. However, the driver is attempting to send a response to the sequence, but it no longer exists on the sequencer.
You will need to show the sequence and driver code for a better explanation.
In reply to cgales :
The relevant code in the driver was:
task uart_driver::main_loop();
uvm_sequence_item item;
uart_pkt_c pkt;
forever begin
seq_item_port.get(item);
void'($cast(pkt, item));
if(pkt==null) `uvm_fatal(get_name(), "casting failed or item returned null")
if(pkt.dir==TX) tx_lock.get();
else
rx_lock.get();
fork
begin
automatic uart_pkt_c req, rsp;
req = pkt;
if(req.dir==TX)
send(req);
else
read(req);
$cast(rsp, req.clone());
rsp.set_id_info(req);
seq_item_port.put(rsp);
if(req.dir==TX)
tx_lock.put();
else
rx_lock.put();
end
join_none
end
endtask
sequene code:
class uart_base_sequence extends uvm_sequence;
`uvm_object_utils(uart_base_sequence)
local uart_pkt_c pkt; //reuse the constraint solver
function new(string name = "uart_base_sequence");
super.new(name);
pkt = uart_pkt_c::type_id::create(get_name(),,get_full_name());
endfunction : new
virtual function void set_name (string name);
super.set_name(name);
pkt.set_name(name);
endfunction
virtual task body();
`uvm_info(get_type_name(), "Call uart seq", UVM_LOW)
`uvm_do_with(req, {data == 3; data_width == `DATA_WIDTH_8BIT; dir == TX; burst_length == 1;})
endtask : body
endclass
`endif
The driver code is taken from a uart example in git.
It looks like that there in no code which end the item… so I guess it’s the problem.
I can use instead get_next_item, and item_done.